1 #ifndef __ALPHA_T2__H__ 2 #define __ALPHA_T2__H__ 3 4 /* Fit everything into one 128MB HAE window. */ 5 #define T2_ONE_HAE_WINDOW 1 6 7 #include <linux/types.h> 8 #include <linux/spinlock.h> 9 #include <asm/compiler.h> 10 11 /* 12 * T2 is the internal name for the core logic chipset which provides 13 * memory controller and PCI access for the SABLE-based systems. 14 * 15 * This file is based on: 16 * 17 * SABLE I/O Specification 18 * Revision/Update Information: 1.3 19 * 20 * jestabro@amt.tay1.dec.com Initial Version. 21 * 22 */ 23 24 #define T2_MEM_R1_MASK 0x07ffffff /* Mem sparse region 1 mask is 27 bits */ 25 26 /* GAMMA-SABLE is a SABLE with EV5-based CPUs */ 27 /* All LYNX machines, EV4 or EV5, use the GAMMA bias also */ 28 #define _GAMMA_BIAS 0x8000000000UL 29 30 #if defined(CONFIG_ALPHA_GENERIC) 31 #define GAMMA_BIAS alpha_mv.sys.t2.gamma_bias 32 #elif defined(CONFIG_ALPHA_GAMMA) 33 #define GAMMA_BIAS _GAMMA_BIAS 34 #else 35 #define GAMMA_BIAS 0 36 #endif 37 38 /* 39 * Memory spaces: 40 */ 41 #define T2_CONF (IDENT_ADDR + GAMMA_BIAS + 0x390000000UL) 42 #define T2_IO (IDENT_ADDR + GAMMA_BIAS + 0x3a0000000UL) 43 #define T2_SPARSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x200000000UL) 44 #define T2_DENSE_MEM (IDENT_ADDR + GAMMA_BIAS + 0x3c0000000UL) 45 46 #define T2_IOCSR (IDENT_ADDR + GAMMA_BIAS + 0x38e000000UL) 47 #define T2_CERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000020UL) 48 #define T2_CERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000040UL) 49 #define T2_CERR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000060UL) 50 #define T2_PERR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000080UL) 51 #define T2_PERR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000a0UL) 52 #define T2_PSCR (IDENT_ADDR + GAMMA_BIAS + 0x38e0000c0UL) 53 #define T2_HAE_1 (IDENT_ADDR + GAMMA_BIAS + 0x38e0000e0UL) 54 #define T2_HAE_2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000100UL) 55 #define T2_HBASE (IDENT_ADDR + GAMMA_BIAS + 0x38e000120UL) 56 #define T2_WBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000140UL) 57 #define T2_WMASK1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000160UL) 58 #define T2_TBASE1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000180UL) 59 #define T2_WBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001a0UL) 60 #define T2_WMASK2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001c0UL) 61 #define T2_TBASE2 (IDENT_ADDR + GAMMA_BIAS + 0x38e0001e0UL) 62 #define T2_TLBBR (IDENT_ADDR + GAMMA_BIAS + 0x38e000200UL) 63 #define T2_IVR (IDENT_ADDR + GAMMA_BIAS + 0x38e000220UL) 64 #define T2_HAE_3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000240UL) 65 #define T2_HAE_4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000260UL) 66 67 /* The CSRs below are T3/T4 only */ 68 #define T2_WBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000280UL) 69 #define T2_WMASK3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002a0UL) 70 #define T2_TBASE3 (IDENT_ADDR + GAMMA_BIAS + 0x38e0002c0UL) 71 72 #define T2_TDR0 (IDENT_ADDR + GAMMA_BIAS + 0x38e000300UL) 73 #define T2_TDR1 (IDENT_ADDR + GAMMA_BIAS + 0x38e000320UL) 74 #define T2_TDR2 (IDENT_ADDR + GAMMA_BIAS + 0x38e000340UL) 75 #define T2_TDR3 (IDENT_ADDR + GAMMA_BIAS + 0x38e000360UL) 76 #define T2_TDR4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000380UL) 77 #define T2_TDR5 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003a0UL) 78 #define T2_TDR6 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003c0UL) 79 #define T2_TDR7 (IDENT_ADDR + GAMMA_BIAS + 0x38e0003e0UL) 80 81 #define T2_WBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000400UL) 82 #define T2_WMASK4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000420UL) 83 #define T2_TBASE4 (IDENT_ADDR + GAMMA_BIAS + 0x38e000440UL) 84 85 #define T2_AIR (IDENT_ADDR + GAMMA_BIAS + 0x38e000460UL) 86 #define T2_VAR (IDENT_ADDR + GAMMA_BIAS + 0x38e000480UL) 87 #define T2_DIR (IDENT_ADDR + GAMMA_BIAS + 0x38e0004a0UL) 88 #define T2_ICE (IDENT_ADDR + GAMMA_BIAS + 0x38e0004c0UL) 89 90 #ifndef T2_ONE_HAE_WINDOW 91 #define T2_HAE_ADDRESS T2_HAE_1 92 #endif 93 94 /* T2 CSRs are in the non-cachable primary IO space from 3.8000.0000 to 95 3.8fff.ffff 96 * 97 * +--------------+ 3 8000 0000 98 * | CPU 0 CSRs | 99 * +--------------+ 3 8100 0000 100 * | CPU 1 CSRs | 101 * +--------------+ 3 8200 0000 102 * | CPU 2 CSRs | 103 * +--------------+ 3 8300 0000 104 * | CPU 3 CSRs | 105 * +--------------+ 3 8400 0000 106 * | CPU Reserved | 107 * +--------------+ 3 8700 0000 108 * | Mem Reserved | 109 * +--------------+ 3 8800 0000 110 * | Mem 0 CSRs | 111 * +--------------+ 3 8900 0000 112 * | Mem 1 CSRs | 113 * +--------------+ 3 8a00 0000 114 * | Mem 2 CSRs | 115 * +--------------+ 3 8b00 0000 116 * | Mem 3 CSRs | 117 * +--------------+ 3 8c00 0000 118 * | Mem Reserved | 119 * +--------------+ 3 8e00 0000 120 * | PCI Bridge | 121 * +--------------+ 3 8f00 0000 122 * | Expansion IO | 123 * +--------------+ 3 9000 0000 124 * 125 * 126 */ 127 #define T2_CPU0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x380000000L) 128 #define T2_CPU1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x381000000L) 129 #define T2_CPU2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x382000000L) 130 #define T2_CPU3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x383000000L) 131 132 #define T2_CPUn_BASE(n) (T2_CPU0_BASE + (((n)&3) * 0x001000000L)) 133 134 #define T2_MEM0_BASE (IDENT_ADDR + GAMMA_BIAS + 0x388000000L) 135 #define T2_MEM1_BASE (IDENT_ADDR + GAMMA_BIAS + 0x389000000L) 136 #define T2_MEM2_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38a000000L) 137 #define T2_MEM3_BASE (IDENT_ADDR + GAMMA_BIAS + 0x38b000000L) 138 139 140 /* 141 * Sable CPU Module CSRS 142 * 143 * These are CSRs for hardware other than the CPU chip on the CPU module. 144 * The CPU module has Backup Cache control logic, Cbus control logic, and 145 * interrupt control logic on it. There is a duplicate tag store to speed 146 * up maintaining cache coherency. 147 */ 148 149 struct sable_cpu_csr { 150 unsigned long bcc; long fill_00[3]; /* Backup Cache Control */ 151 unsigned long bcce; long fill_01[3]; /* Backup Cache Correctable Error */ 152 unsigned long bccea; long fill_02[3]; /* B-Cache Corr Err Address Latch */ 153 unsigned long bcue; long fill_03[3]; /* B-Cache Uncorrectable Error */ 154 unsigned long bcuea; long fill_04[3]; /* B-Cache Uncorr Err Addr Latch */ 155 unsigned long dter; long fill_05[3]; /* Duplicate Tag Error */ 156 unsigned long cbctl; long fill_06[3]; /* CBus Control */ 157 unsigned long cbe; long fill_07[3]; /* CBus Error */ 158 unsigned long cbeal; long fill_08[3]; /* CBus Error Addr Latch low */ 159 unsigned long cbeah; long fill_09[3]; /* CBus Error Addr Latch high */ 160 unsigned long pmbx; long fill_10[3]; /* Processor Mailbox */ 161 unsigned long ipir; long fill_11[3]; /* Inter-Processor Int Request */ 162 unsigned long sic; long fill_12[3]; /* System Interrupt Clear */ 163 unsigned long adlk; long fill_13[3]; /* Address Lock (LDxL/STxC) */ 164 unsigned long madrl; long fill_14[3]; /* CBus Miss Address */ 165 unsigned long rev; long fill_15[3]; /* CMIC Revision */ 166 }; 167 168 /* 169 * Data structure for handling T2 machine checks: 170 */ 171 struct el_t2_frame_header { 172 unsigned int elcf_fid; /* Frame ID (from above) */ 173 unsigned int elcf_size; /* Size of frame in bytes */ 174 }; 175 176 struct el_t2_procdata_mcheck { 177 unsigned long elfmc_paltemp[32]; /* PAL TEMP REGS. */ 178 /* EV4-specific fields */ 179 unsigned long elfmc_exc_addr; /* Addr of excepting insn. */ 180 unsigned long elfmc_exc_sum; /* Summary of arith traps. */ 181 unsigned long elfmc_exc_mask; /* Exception mask (from exc_sum). */ 182 unsigned long elfmc_iccsr; /* IBox hardware enables. */ 183 unsigned long elfmc_pal_base; /* Base address for PALcode. */ 184 unsigned long elfmc_hier; /* Hardware Interrupt Enable. */ 185 unsigned long elfmc_hirr; /* Hardware Interrupt Request. */ 186 unsigned long elfmc_mm_csr; /* D-stream fault info. */ 187 unsigned long elfmc_dc_stat; /* D-cache status (ECC/Parity Err). */ 188 unsigned long elfmc_dc_addr; /* EV3 Phys Addr for ECC/DPERR. */ 189 unsigned long elfmc_abox_ctl; /* ABox Control Register. */ 190 unsigned long elfmc_biu_stat; /* BIU Status. */ 191 unsigned long elfmc_biu_addr; /* BUI Address. */ 192 unsigned long elfmc_biu_ctl; /* BIU Control. */ 193 unsigned long elfmc_fill_syndrome; /* For correcting ECC errors. */ 194 unsigned long elfmc_fill_addr;/* Cache block which was being read. */ 195 unsigned long elfmc_va; /* Effective VA of fault or miss. */ 196 unsigned long elfmc_bc_tag; /* Backup Cache Tag Probe Results. */ 197 }; 198 199 /* 200 * Sable processor specific Machine Check Data segment. 201 */ 202 203 struct el_t2_logout_header { 204 unsigned int elfl_size; /* size in bytes of logout area. */ 205 unsigned int elfl_sbz1:31; /* Should be zero. */ 206 unsigned int elfl_retry:1; /* Retry flag. */ 207 unsigned int elfl_procoffset; /* Processor-specific offset. */ 208 unsigned int elfl_sysoffset; /* Offset of system-specific. */ 209 unsigned int elfl_error_type; /* PAL error type code. */ 210 unsigned int elfl_frame_rev; /* PAL Frame revision. */ 211 }; 212 struct el_t2_sysdata_mcheck { 213 unsigned long elcmc_bcc; /* CSR 0 */ 214 unsigned long elcmc_bcce; /* CSR 1 */ 215 unsigned long elcmc_bccea; /* CSR 2 */ 216 unsigned long elcmc_bcue; /* CSR 3 */ 217 unsigned long elcmc_bcuea; /* CSR 4 */ 218 unsigned long elcmc_dter; /* CSR 5 */ 219 unsigned long elcmc_cbctl; /* CSR 6 */ 220 unsigned long elcmc_cbe; /* CSR 7 */ 221 unsigned long elcmc_cbeal; /* CSR 8 */ 222 unsigned long elcmc_cbeah; /* CSR 9 */ 223 unsigned long elcmc_pmbx; /* CSR 10 */ 224 unsigned long elcmc_ipir; /* CSR 11 */ 225 unsigned long elcmc_sic; /* CSR 12 */ 226 unsigned long elcmc_adlk; /* CSR 13 */ 227 unsigned long elcmc_madrl; /* CSR 14 */ 228 unsigned long elcmc_crrev4; /* CSR 15 */ 229 }; 230 231 /* 232 * Sable memory error frame - sable pfms section 3.42 233 */ 234 struct el_t2_data_memory { 235 struct el_t2_frame_header elcm_hdr; /* ID$MEM-FERR = 0x08 */ 236 unsigned int elcm_module; /* Module id. */ 237 unsigned int elcm_res04; /* Reserved. */ 238 unsigned long elcm_merr; /* CSR0: Error Reg 1. */ 239 unsigned long elcm_mcmd1; /* CSR1: Command Trap 1. */ 240 unsigned long elcm_mcmd2; /* CSR2: Command Trap 2. */ 241 unsigned long elcm_mconf; /* CSR3: Configuration. */ 242 unsigned long elcm_medc1; /* CSR4: EDC Status 1. */ 243 unsigned long elcm_medc2; /* CSR5: EDC Status 2. */ 244 unsigned long elcm_medcc; /* CSR6: EDC Control. */ 245 unsigned long elcm_msctl; /* CSR7: Stream Buffer Control. */ 246 unsigned long elcm_mref; /* CSR8: Refresh Control. */ 247 unsigned long elcm_filter; /* CSR9: CRD Filter Control. */ 248 }; 249 250 251 /* 252 * Sable other CPU error frame - sable pfms section 3.43 253 */ 254 struct el_t2_data_other_cpu { 255 short elco_cpuid; /* CPU ID */ 256 short elco_res02[3]; 257 unsigned long elco_bcc; /* CSR 0 */ 258 unsigned long elco_bcce; /* CSR 1 */ 259 unsigned long elco_bccea; /* CSR 2 */ 260 unsigned long elco_bcue; /* CSR 3 */ 261 unsigned long elco_bcuea; /* CSR 4 */ 262 unsigned long elco_dter; /* CSR 5 */ 263 unsigned long elco_cbctl; /* CSR 6 */ 264 unsigned long elco_cbe; /* CSR 7 */ 265 unsigned long elco_cbeal; /* CSR 8 */ 266 unsigned long elco_cbeah; /* CSR 9 */ 267 unsigned long elco_pmbx; /* CSR 10 */ 268 unsigned long elco_ipir; /* CSR 11 */ 269 unsigned long elco_sic; /* CSR 12 */ 270 unsigned long elco_adlk; /* CSR 13 */ 271 unsigned long elco_madrl; /* CSR 14 */ 272 unsigned long elco_crrev4; /* CSR 15 */ 273 }; 274 275 /* 276 * Sable other CPU error frame - sable pfms section 3.44 277 */ 278 struct el_t2_data_t2{ 279 struct el_t2_frame_header elct_hdr; /* ID$T2-FRAME */ 280 unsigned long elct_iocsr; /* IO Control and Status Register */ 281 unsigned long elct_cerr1; /* Cbus Error Register 1 */ 282 unsigned long elct_cerr2; /* Cbus Error Register 2 */ 283 unsigned long elct_cerr3; /* Cbus Error Register 3 */ 284 unsigned long elct_perr1; /* PCI Error Register 1 */ 285 unsigned long elct_perr2; /* PCI Error Register 2 */ 286 unsigned long elct_hae0_1; /* High Address Extension Register 1 */ 287 unsigned long elct_hae0_2; /* High Address Extension Register 2 */ 288 unsigned long elct_hbase; /* High Base Register */ 289 unsigned long elct_wbase1; /* Window Base Register 1 */ 290 unsigned long elct_wmask1; /* Window Mask Register 1 */ 291 unsigned long elct_tbase1; /* Translated Base Register 1 */ 292 unsigned long elct_wbase2; /* Window Base Register 2 */ 293 unsigned long elct_wmask2; /* Window Mask Register 2 */ 294 unsigned long elct_tbase2; /* Translated Base Register 2 */ 295 unsigned long elct_tdr0; /* TLB Data Register 0 */ 296 unsigned long elct_tdr1; /* TLB Data Register 1 */ 297 unsigned long elct_tdr2; /* TLB Data Register 2 */ 298 unsigned long elct_tdr3; /* TLB Data Register 3 */ 299 unsigned long elct_tdr4; /* TLB Data Register 4 */ 300 unsigned long elct_tdr5; /* TLB Data Register 5 */ 301 unsigned long elct_tdr6; /* TLB Data Register 6 */ 302 unsigned long elct_tdr7; /* TLB Data Register 7 */ 303 }; 304 305 /* 306 * Sable error log data structure - sable pfms section 3.40 307 */ 308 struct el_t2_data_corrected { 309 unsigned long elcpb_biu_stat; 310 unsigned long elcpb_biu_addr; 311 unsigned long elcpb_biu_ctl; 312 unsigned long elcpb_fill_syndrome; 313 unsigned long elcpb_fill_addr; 314 unsigned long elcpb_bc_tag; 315 }; 316 317 /* 318 * Sable error log data structure 319 * Note there are 4 memory slots on sable (see t2.h) 320 */ 321 struct el_t2_frame_mcheck { 322 struct el_t2_frame_header elfmc_header; /* ID$P-FRAME_MCHECK */ 323 struct el_t2_logout_header elfmc_hdr; 324 struct el_t2_procdata_mcheck elfmc_procdata; 325 struct el_t2_sysdata_mcheck elfmc_sysdata; 326 struct el_t2_data_t2 elfmc_t2data; 327 struct el_t2_data_memory elfmc_memdata[4]; 328 struct el_t2_frame_header elfmc_footer; /* empty */ 329 }; 330 331 332 /* 333 * Sable error log data structures on memory errors 334 */ 335 struct el_t2_frame_corrected { 336 struct el_t2_frame_header elfcc_header; /* ID$P-BC-COR */ 337 struct el_t2_logout_header elfcc_hdr; 338 struct el_t2_data_corrected elfcc_procdata; 339 /* struct el_t2_data_t2 elfcc_t2data; */ 340 /* struct el_t2_data_memory elfcc_memdata[4]; */ 341 struct el_t2_frame_header elfcc_footer; /* empty */ 342 }; 343 344 345 #ifdef __KERNEL__ 346 347 #ifndef __EXTERN_INLINE 348 #define __EXTERN_INLINE extern inline 349 #define __IO_EXTERN_INLINE 350 #endif 351 352 /* 353 * I/O functions: 354 * 355 * T2 (the core logic PCI/memory support chipset for the SABLE 356 * series of processors uses a sparse address mapping scheme to 357 * get at PCI memory and I/O. 358 */ 359 360 #define vip volatile int * 361 #define vuip volatile unsigned int * 362 363 extern inline u8 t2_inb(unsigned long addr) 364 { 365 long result = *(vip) ((addr << 5) + T2_IO + 0x00); 366 return __kernel_extbl(result, addr & 3); 367 } 368 369 extern inline void t2_outb(u8 b, unsigned long addr) 370 { 371 unsigned long w; 372 373 w = __kernel_insbl(b, addr & 3); 374 *(vuip) ((addr << 5) + T2_IO + 0x00) = w; 375 mb(); 376 } 377 378 extern inline u16 t2_inw(unsigned long addr) 379 { 380 long result = *(vip) ((addr << 5) + T2_IO + 0x08); 381 return __kernel_extwl(result, addr & 3); 382 } 383 384 extern inline void t2_outw(u16 b, unsigned long addr) 385 { 386 unsigned long w; 387 388 w = __kernel_inswl(b, addr & 3); 389 *(vuip) ((addr << 5) + T2_IO + 0x08) = w; 390 mb(); 391 } 392 393 extern inline u32 t2_inl(unsigned long addr) 394 { 395 return *(vuip) ((addr << 5) + T2_IO + 0x18); 396 } 397 398 extern inline void t2_outl(u32 b, unsigned long addr) 399 { 400 *(vuip) ((addr << 5) + T2_IO + 0x18) = b; 401 mb(); 402 } 403 404 405 /* 406 * Memory functions. 407 * 408 * For reading and writing 8 and 16 bit quantities we need to 409 * go through one of the three sparse address mapping regions 410 * and use the HAE_MEM CSR to provide some bits of the address. 411 * The following few routines use only sparse address region 1 412 * which gives 1Gbyte of accessible space which relates exactly 413 * to the amount of PCI memory mapping *into* system address space. 414 * See p 6-17 of the specification but it looks something like this: 415 * 416 * 21164 Address: 417 * 418 * 3 2 1 419 * 9876543210987654321098765432109876543210 420 * 1ZZZZ0.PCI.QW.Address............BBLL 421 * 422 * ZZ = SBZ 423 * BB = Byte offset 424 * LL = Transfer length 425 * 426 * PCI Address: 427 * 428 * 3 2 1 429 * 10987654321098765432109876543210 430 * HHH....PCI.QW.Address........ 00 431 * 432 * HHH = 31:29 HAE_MEM CSR 433 * 434 */ 435 436 #ifdef T2_ONE_HAE_WINDOW 437 #define t2_set_hae 438 #else 439 #define t2_set_hae { \ 440 unsigned long msb = addr >> 27; \ 441 addr &= T2_MEM_R1_MASK; \ 442 set_hae(msb); \ 443 } 444 #endif 445 446 /* 447 * NOTE: take T2_DENSE_MEM off in each readX/writeX routine, since 448 * they may be called directly, rather than through the 449 * ioreadNN/iowriteNN routines. 450 */ 451 452 __EXTERN_INLINE u8 t2_readb(const volatile void __iomem *xaddr) 453 { 454 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 455 unsigned long result; 456 457 t2_set_hae; 458 459 result = *(vip) ((addr << 5) + T2_SPARSE_MEM + 0x00); 460 return __kernel_extbl(result, addr & 3); 461 } 462 463 __EXTERN_INLINE u16 t2_readw(const volatile void __iomem *xaddr) 464 { 465 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 466 unsigned long result; 467 468 t2_set_hae; 469 470 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08); 471 return __kernel_extwl(result, addr & 3); 472 } 473 474 /* 475 * On SABLE with T2, we must use SPARSE memory even for 32-bit access, 476 * because we cannot access all of DENSE without changing its HAE. 477 */ 478 __EXTERN_INLINE u32 t2_readl(const volatile void __iomem *xaddr) 479 { 480 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 481 unsigned long result; 482 483 t2_set_hae; 484 485 result = *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18); 486 return result & 0xffffffffUL; 487 } 488 489 __EXTERN_INLINE u64 t2_readq(const volatile void __iomem *xaddr) 490 { 491 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 492 unsigned long r0, r1, work; 493 494 t2_set_hae; 495 496 work = (addr << 5) + T2_SPARSE_MEM + 0x18; 497 r0 = *(vuip)(work); 498 r1 = *(vuip)(work + (4 << 5)); 499 return r1 << 32 | r0; 500 } 501 502 __EXTERN_INLINE void t2_writeb(u8 b, volatile void __iomem *xaddr) 503 { 504 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 505 unsigned long w; 506 507 t2_set_hae; 508 509 w = __kernel_insbl(b, addr & 3); 510 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x00) = w; 511 } 512 513 __EXTERN_INLINE void t2_writew(u16 b, volatile void __iomem *xaddr) 514 { 515 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 516 unsigned long w; 517 518 t2_set_hae; 519 520 w = __kernel_inswl(b, addr & 3); 521 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x08) = w; 522 } 523 524 /* 525 * On SABLE with T2, we must use SPARSE memory even for 32-bit access, 526 * because we cannot access all of DENSE without changing its HAE. 527 */ 528 __EXTERN_INLINE void t2_writel(u32 b, volatile void __iomem *xaddr) 529 { 530 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 531 532 t2_set_hae; 533 534 *(vuip) ((addr << 5) + T2_SPARSE_MEM + 0x18) = b; 535 } 536 537 __EXTERN_INLINE void t2_writeq(u64 b, volatile void __iomem *xaddr) 538 { 539 unsigned long addr = (unsigned long) xaddr - T2_DENSE_MEM; 540 unsigned long work; 541 542 t2_set_hae; 543 544 work = (addr << 5) + T2_SPARSE_MEM + 0x18; 545 *(vuip)work = b; 546 *(vuip)(work + (4 << 5)) = b >> 32; 547 } 548 549 __EXTERN_INLINE void __iomem *t2_ioportmap(unsigned long addr) 550 { 551 return (void __iomem *)(addr + T2_IO); 552 } 553 554 __EXTERN_INLINE void __iomem *t2_ioremap(unsigned long addr, 555 unsigned long size) 556 { 557 return (void __iomem *)(addr + T2_DENSE_MEM); 558 } 559 560 __EXTERN_INLINE int t2_is_ioaddr(unsigned long addr) 561 { 562 return (long)addr >= 0; 563 } 564 565 __EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr) 566 { 567 return (unsigned long)addr >= T2_DENSE_MEM; 568 } 569 570 /* New-style ioread interface. The mmio routines are so ugly for T2 that 571 it doesn't make sense to merge the pio and mmio routines. */ 572 573 #define IOPORT(OS, NS) \ 574 __EXTERN_INLINE unsigned int t2_ioread##NS(void __iomem *xaddr) \ 575 { \ 576 if (t2_is_mmio(xaddr)) \ 577 return t2_read##OS(xaddr); \ 578 else \ 579 return t2_in##OS((unsigned long)xaddr - T2_IO); \ 580 } \ 581 __EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr) \ 582 { \ 583 if (t2_is_mmio(xaddr)) \ 584 t2_write##OS(b, xaddr); \ 585 else \ 586 t2_out##OS(b, (unsigned long)xaddr - T2_IO); \ 587 } 588 589 IOPORT(b, 8) 590 IOPORT(w, 16) 591 IOPORT(l, 32) 592 593 #undef IOPORT 594 595 #undef vip 596 #undef vuip 597 598 #undef __IO_PREFIX 599 #define __IO_PREFIX t2 600 #define t2_trivial_rw_bw 0 601 #define t2_trivial_rw_lq 0 602 #define t2_trivial_io_bw 0 603 #define t2_trivial_io_lq 0 604 #define t2_trivial_iounmap 1 605 #include <asm/io_trivial.h> 606 607 #ifdef __IO_EXTERN_INLINE 608 #undef __EXTERN_INLINE 609 #undef __IO_EXTERN_INLINE 610 #endif 611 612 #endif /* __KERNEL__ */ 613 614 #endif /* __ALPHA_T2__H__ */ 615