1.. SPDX-License-Identifier: GPL-2.0 2 3======================================= 4Known limitations of CPU virtualization 5======================================= 6 7Whenever perfect emulation of a CPU feature is impossible or too hard, KVM 8has to choose between not implementing the feature at all or introducing 9behavioral differences between virtual machines and bare metal systems. 10 11This file documents some of the known limitations that KVM has in 12virtualizing CPU features. 13 14x86 15=== 16 17``KVM_GET_SUPPORTED_CPUID`` issues 18---------------------------------- 19 20x87 features 21~~~~~~~~~~~~ 22 23Unlike most other CPUID feature bits, CPUID[EAX=7,ECX=0]:EBX[6] 24(FDP_EXCPTN_ONLY) and CPUID[EAX=7,ECX=0]:EBX]13] (ZERO_FCS_FDS) are 25clear if the features are present and set if the features are not present. 26 27Clearing these bits in CPUID has no effect on the operation of the guest; 28if these bits are set on hardware, the features will not be present on 29any virtual machine that runs on that hardware. 30 31**Workaround:** It is recommended to always set these bits in guest CPUID. 32Note however that any software (e.g ``WIN87EM.DLL``) expecting these features 33to be present likely predates these CPUID feature bits, and therefore 34doesn't know to check for them anyway. 35 36``KVM_SET_VCPU_EVENTS`` issue 37----------------------------- 38 39Invalid KVM_SET_VCPU_EVENTS input with respect to error codes *may* result in 40failed VM-Entry on Intel CPUs. Pre-CET Intel CPUs require that exception 41injection through the VMCS correctly set the "error code valid" flag, e.g. 42require the flag be set when injecting a #GP, clear when injecting a #UD, 43clear when injecting a soft exception, etc. Intel CPUs that enumerate 44IA32_VMX_BASIC[56] as '1' relax VMX's consistency checks, and AMD CPUs have no 45restrictions whatsoever. KVM_SET_VCPU_EVENTS doesn't sanity check the vector 46versus "has_error_code", i.e. KVM's ABI follows AMD behavior. 47 48Nested virtualization features 49------------------------------ 50 51On AMD CPUs, when GIF is cleared, #DB exceptions or traps due to a breakpoint 52register match are ignored and discarded by the CPU. The CPU relies on the VMM 53to fully virtualize this behavior, even when vGIF is enabled for the guest 54(i.e. vGIF=0 does not cause the CPU to drop #DBs when the guest is running). 55KVM does not virtualize this behavior as the complexity is unjustified given 56the rarity of the use case. One way to handle this would be for KVM to 57intercept the #DB, temporarily disable the breakpoint, single-step over the 58instruction, then re-enable the breakpoint. 59 60x2APIC 61------ 62When KVM_X2APIC_API_USE_32BIT_IDS is enabled, KVM activates a hack/quirk that 63allows sending events to a single vCPU using its x2APIC ID even if the target 64vCPU has legacy xAPIC enabled, e.g. to bring up hotplugged vCPUs via INIT-SIPI 65on VMs with > 255 vCPUs. A side effect of the quirk is that, if multiple vCPUs 66have the same physical APIC ID, KVM will deliver events targeting that APIC ID 67only to the vCPU with the lowest vCPU ID. If KVM_X2APIC_API_USE_32BIT_IDS is 68not enabled, KVM follows x86 architecture when processing interrupts (all vCPUs 69matching the target APIC ID receive the interrupt). 70 71MTRRs 72----- 73KVM does not virtualize guest MTRR memory types. KVM emulates accesses to MTRR 74MSRs, i.e. {RD,WR}MSR in the guest will behave as expected, but KVM does not 75honor guest MTRRs when determining the effective memory type, and instead 76treats all of guest memory as having Writeback (WB) MTRRs. 77 78CR0.CD 79------ 80KVM does not virtualize CR0.CD on Intel CPUs. Similar to MTRR MSRs, KVM 81emulates CR0.CD accesses so that loads and stores from/to CR0 behave as 82expected, but setting CR0.CD=1 has no impact on the cachaeability of guest 83memory. 84 85Note, this erratum does not affect AMD CPUs, which fully virtualize CR0.CD in 86hardware, i.e. put the CPU caches into "no fill" mode when CR0.CD=1, even when 87running in the guest.