1.. SPDX-License-Identifier: GPL-2.0 2 3========================= 4MPIC interrupt controller 5========================= 6 7Device types supported: 8 9 - KVM_DEV_TYPE_FSL_MPIC_20 Freescale MPIC v2.0 10 - KVM_DEV_TYPE_FSL_MPIC_42 Freescale MPIC v4.2 11 12Only one MPIC instance, of any type, may be instantiated. The created 13MPIC will act as the system interrupt controller, connecting to each 14vcpu's interrupt inputs. 15 16Groups: 17 KVM_DEV_MPIC_GRP_MISC 18 Attributes: 19 20 KVM_DEV_MPIC_BASE_ADDR (rw, 64-bit) 21 Base address of the 256 KiB MPIC register space. Must be 22 naturally aligned. A value of zero disables the mapping. 23 Reset value is zero. 24 25 KVM_DEV_MPIC_GRP_REGISTER (rw, 32-bit) 26 Access an MPIC register, as if the access were made from the guest. 27 "attr" is the byte offset into the MPIC register space. Accesses 28 must be 4-byte aligned. 29 30 MSIs may be signaled by using this attribute group to write 31 to the relevant MSIIR. 32 33 KVM_DEV_MPIC_GRP_IRQ_ACTIVE (rw, 32-bit) 34 IRQ input line for each standard openpic source. 0 is inactive and 1 35 is active, regardless of interrupt sense. 36 37 For edge-triggered interrupts: Writing 1 is considered an activating 38 edge, and writing 0 is ignored. Reading returns 1 if a previously 39 signaled edge has not been acknowledged, and 0 otherwise. 40 41 "attr" is the IRQ number. IRQ numbers for standard sources are the 42 byte offset of the relevant IVPR from EIVPR0, divided by 32. 43 44IRQ Routing: 45 46 The MPIC emulation supports IRQ routing. Only a single MPIC device can 47 be instantiated. Once that device has been created, it's available as 48 irqchip id 0. 49 50 This irqchip 0 has 256 interrupt pins, which expose the interrupts in 51 the main array of interrupt sources (a.k.a. "SRC" interrupts). 52 53 The numbering is the same as the MPIC device tree binding -- based on 54 the register offset from the beginning of the sources array, without 55 regard to any subdivisions in chip documentation such as "internal" 56 or "external" interrupts. 57 58 Access to non-SRC interrupts is not implemented through IRQ routing mechanisms. 59