1========================= 2NXP SJA1105 switch driver 3========================= 4 5Overview 6======== 7 8The NXP SJA1105 is a family of 6 devices: 9 10- SJA1105E: First generation, no TTEthernet 11- SJA1105T: First generation, TTEthernet 12- SJA1105P: Second generation, no TTEthernet, no SGMII 13- SJA1105Q: Second generation, TTEthernet, no SGMII 14- SJA1105R: Second generation, no TTEthernet, SGMII 15- SJA1105S: Second generation, TTEthernet, SGMII 16 17These are SPI-managed automotive switches, with all ports being gigabit 18capable, and supporting MII/RMII/RGMII and optionally SGMII on one port. 19 20Being automotive parts, their configuration interface is geared towards 21set-and-forget use, with minimal dynamic interaction at runtime. They 22require a static configuration to be composed by software and packed 23with CRC and table headers, and sent over SPI. 24 25The static configuration is composed of several configuration tables. Each 26table takes a number of entries. Some configuration tables can be (partially) 27reconfigured at runtime, some not. Some tables are mandatory, some not: 28 29============================= ================== ============================= 30Table Mandatory Reconfigurable 31============================= ================== ============================= 32Schedule no no 33Schedule entry points if Scheduling no 34VL Lookup no no 35VL Policing if VL Lookup no 36VL Forwarding if VL Lookup no 37L2 Lookup no no 38L2 Policing yes no 39VLAN Lookup yes yes 40L2 Forwarding yes partially (fully on P/Q/R/S) 41MAC Config yes partially (fully on P/Q/R/S) 42Schedule Params if Scheduling no 43Schedule Entry Points Params if Scheduling no 44VL Forwarding Params if VL Forwarding no 45L2 Lookup Params no partially (fully on P/Q/R/S) 46L2 Forwarding Params yes no 47Clock Sync Params no no 48AVB Params no no 49General Params yes partially 50Retagging no yes 51xMII Params yes no 52SGMII no yes 53============================= ================== ============================= 54 55 56Also the configuration is write-only (software cannot read it back from the 57switch except for very few exceptions). 58 59The driver creates a static configuration at probe time, and keeps it at 60all times in memory, as a shadow for the hardware state. When required to 61change a hardware setting, the static configuration is also updated. 62If that changed setting can be transmitted to the switch through the dynamic 63reconfiguration interface, it is; otherwise the switch is reset and 64reprogrammed with the updated static configuration. 65 66Traffic support 67=============== 68 69The switches do not support switch tagging in hardware. But they do support 70customizing the TPID by which VLAN traffic is identified as such. The switch 71driver is leveraging ``CONFIG_NET_DSA_TAG_8021Q`` by requesting that special 72VLANs (with a custom TPID of ``ETH_P_EDSA`` instead of ``ETH_P_8021Q``) are 73installed on its ports when not in ``vlan_filtering`` mode. This does not 74interfere with the reception and transmission of real 802.1Q-tagged traffic, 75because the switch does no longer parse those packets as VLAN after the TPID 76change. 77The TPID is restored when ``vlan_filtering`` is requested by the user through 78the bridge layer, and general IP termination becomes no longer possible through 79the switch netdevices in this mode. 80 81The switches have two programmable filters for link-local destination MACs. 82These are used to trap BPDUs and PTP traffic to the master netdevice, and are 83further used to support STP and 1588 ordinary clock/boundary clock 84functionality. 85 86The following traffic modes are supported over the switch netdevices: 87 88+--------------------+------------+------------------+------------------+ 89| | Standalone | Bridged with | Bridged with | 90| | ports | vlan_filtering 0 | vlan_filtering 1 | 91+====================+============+==================+==================+ 92| Regular traffic | Yes | Yes | No (use master) | 93+--------------------+------------+------------------+------------------+ 94| Management traffic | Yes | Yes | Yes | 95| (BPDU, PTP) | | | | 96+--------------------+------------+------------------+------------------+ 97 98Switching features 99================== 100 101The driver supports the configuration of L2 forwarding rules in hardware for 102port bridging. The forwarding, broadcast and flooding domain between ports can 103be restricted through two methods: either at the L2 forwarding level (isolate 104one bridge's ports from another's) or at the VLAN port membership level 105(isolate ports within the same bridge). The final forwarding decision taken by 106the hardware is a logical AND of these two sets of rules. 107 108The hardware tags all traffic internally with a port-based VLAN (pvid), or it 109decodes the VLAN information from the 802.1Q tag. Advanced VLAN classification 110is not possible. Once attributed a VLAN tag, frames are checked against the 111port's membership rules and dropped at ingress if they don't match any VLAN. 112This behavior is available when switch ports are enslaved to a bridge with 113``vlan_filtering 1``. 114 115Normally the hardware is not configurable with respect to VLAN awareness, but 116by changing what TPID the switch searches 802.1Q tags for, the semantics of a 117bridge with ``vlan_filtering 0`` can be kept (accept all traffic, tagged or 118untagged), and therefore this mode is also supported. 119 120Segregating the switch ports in multiple bridges is supported (e.g. 2 + 2), but 121all bridges should have the same level of VLAN awareness (either both have 122``vlan_filtering`` 0, or both 1). Also an inevitable limitation of the fact 123that VLAN awareness is global at the switch level is that once a bridge with 124``vlan_filtering`` enslaves at least one switch port, the other un-bridged 125ports are no longer available for standalone traffic termination. 126 127Topology and loop detection through STP is supported. 128 129L2 FDB manipulation (add/delete/dump) is currently possible for the first 130generation devices. Aging time of FDB entries, as well as enabling fully static 131management (no address learning and no flooding of unknown traffic) is not yet 132configurable in the driver. 133 134A special comment about bridging with other netdevices (illustrated with an 135example): 136 137A board has eth0, eth1, swp0@eth1, swp1@eth1, swp2@eth1, swp3@eth1. 138The switch ports (swp0-3) are under br0. 139It is desired that eth0 is turned into another switched port that communicates 140with swp0-3. 141 142If br0 has vlan_filtering 0, then eth0 can simply be added to br0 with the 143intended results. 144If br0 has vlan_filtering 1, then a new br1 interface needs to be created that 145enslaves eth0 and eth1 (the DSA master of the switch ports). This is because in 146this mode, the switch ports beneath br0 are not capable of regular traffic, and 147are only used as a conduit for switchdev operations. 148 149Device Tree bindings and board design 150===================================== 151 152This section references ``Documentation/devicetree/bindings/net/dsa/sja1105.txt`` 153and aims to showcase some potential switch caveats. 154 155RMII PHY role and out-of-band signaling 156--------------------------------------- 157 158In the RMII spec, the 50 MHz clock signals are either driven by the MAC or by 159an external oscillator (but not by the PHY). 160But the spec is rather loose and devices go outside it in several ways. 161Some PHYs go against the spec and may provide an output pin where they source 162the 50 MHz clock themselves, in an attempt to be helpful. 163On the other hand, the SJA1105 is only binary configurable - when in the RMII 164MAC role it will also attempt to drive the clock signal. To prevent this from 165happening it must be put in RMII PHY role. 166But doing so has some unintended consequences. 167In the RMII spec, the PHY can transmit extra out-of-band signals via RXD[1:0]. 168These are practically some extra code words (/J/ and /K/) sent prior to the 169preamble of each frame. The MAC does not have this out-of-band signaling 170mechanism defined by the RMII spec. 171So when the SJA1105 port is put in PHY role to avoid having 2 drivers on the 172clock signal, inevitably an RMII PHY-to-PHY connection is created. The SJA1105 173emulates a PHY interface fully and generates the /J/ and /K/ symbols prior to 174frame preambles, which the real PHY is not expected to understand. So the PHY 175simply encodes the extra symbols received from the SJA1105-as-PHY onto the 176100Base-Tx wire. 177On the other side of the wire, some link partners might discard these extra 178symbols, while others might choke on them and discard the entire Ethernet 179frames that follow along. This looks like packet loss with some link partners 180but not with others. 181The take-away is that in RMII mode, the SJA1105 must be let to drive the 182reference clock if connected to a PHY. 183 184RGMII fixed-link and internal delays 185------------------------------------ 186 187As mentioned in the bindings document, the second generation of devices has 188tunable delay lines as part of the MAC, which can be used to establish the 189correct RGMII timing budget. 190When powered up, these can shift the Rx and Tx clocks with a phase difference 191between 73.8 and 101.7 degrees. 192The catch is that the delay lines need to lock onto a clock signal with a 193stable frequency. This means that there must be at least 2 microseconds of 194silence between the clock at the old vs at the new frequency. Otherwise the 195lock is lost and the delay lines must be reset (powered down and back up). 196In RGMII the clock frequency changes with link speed (125 MHz at 1000 Mbps, 25 197MHz at 100 Mbps and 2.5 MHz at 10 Mbps), and link speed might change during the 198AN process. 199In the situation where the switch port is connected through an RGMII fixed-link 200to a link partner whose link state life cycle is outside the control of Linux 201(such as a different SoC), then the delay lines would remain unlocked (and 202inactive) until there is manual intervention (ifdown/ifup on the switch port). 203The take-away is that in RGMII mode, the switch's internal delays are only 204reliable if the link partner never changes link speeds, or if it does, it does 205so in a way that is coordinated with the switch port (practically, both ends of 206the fixed-link are under control of the same Linux system). 207As to why would a fixed-link interface ever change link speeds: there are 208Ethernet controllers out there which come out of reset in 100 Mbps mode, and 209their driver inevitably needs to change the speed and clock frequency if it's 210required to work at gigabit. 211 212MDIO bus and PHY management 213--------------------------- 214 215The SJA1105 does not have an MDIO bus and does not perform in-band AN either. 216Therefore there is no link state notification coming from the switch device. 217A board would need to hook up the PHYs connected to the switch to any other 218MDIO bus available to Linux within the system (e.g. to the DSA master's MDIO 219bus). Link state management then works by the driver manually keeping in sync 220(over SPI commands) the MAC link speed with the settings negotiated by the PHY. 221