1.. SPDX-License-Identifier: GPL-2.0-only 2 3============= 4AD7606 driver 5============= 6 7ADC driver for Analog Devices Inc. AD7606 and similar devices. The module name 8is ``ad7606``. 9 10Supported devices 11================= 12 13The following chips are supported by this driver: 14 15* `AD7605 <https://www.analog.com/en/products/ad7605.html>`_ 16* `AD7606 <https://www.analog.com/en/products/ad7606.html>`_ 17* `AD7606B <https://www.analog.com/en/products/ad7606b.html>`_ 18* `AD7616 <https://www.analog.com/en/products/ad7616.html>`_ 19 20Supported features 21================== 22 23SPI wiring modes 24---------------- 25 26These ADCs can output data on several SDO lines (1/2/4/8). The driver 27currently supports only 1 SDO line. 28 29Parallel wiring mode 30-------------------- 31 32There is also a parallel interface, with 16 lines (that can be reduced to 8 in 33byte mode). The parallel interface is selected by declaring the device as 34platform in the device tree (with no io-backends node defined, see below). 35 36IIO-backend mode 37---------------- 38 39This mode allows to reach the best sample rates, but it requires an external 40hardware (eg HDL or APU) to handle the low level communication. 41The backend mode is enabled when through the definition of the "io-backends" 42property in the device tree. 43 44The reference configuration for the current implementation of IIO-backend mode 45is the HDL reference provided by ADI: 46https://wiki.analog.com/resources/eval/user-guides/ad7606x-fmc/hdl 47 48This implementation embeds an IIO-backend compatible IP (adi-axi-adc) and a PWM 49connected to the conversion trigger pin. 50 51.. code-block:: 52 53 +---+ +---------------------------- 54 | | +-------+ |AD76xx 55 | A | controls | | | 56 | D |-------------->| PWM |-------------->| cnvst 57 | 7 | | | | 58 | 6 | +-------+ | 59 | 0 | controls +-----------+-----------+ | 60 | 6 |---------->| | |<--| frstdata 61 | | | Backend | Backend |<--| busy 62 | D | | Driver | | | 63 | R | | | |-->| clk 64 | I | requests |+---------+| DMA | | 65 | V |----------->| Buffer ||<---- |<=>| DATA 66 | E | |+---------+| | | 67 | R | +-----------+-----------+ | 68 | |-------------------------------------->| reset/configuration gpios 69 +---+ +----------------------------- 70 71 72Software and hardware modes 73--------------------------- 74 75While all the AD7606/AD7616 series parts can be configured using GPIOs, some of 76them can be configured using register. 77 78The chips that support software mode have more values available for configuring 79the device, as well as more settings, and allow to control the range and 80calibration per channel. 81 82The following settings are available per channel in software mode: 83 - Scale 84 85Also, there is a broader choice of oversampling ratios in software mode. 86 87Conversion triggering 88--------------------- 89 90The conversion can be triggered by two distinct ways: 91 92 - A GPIO is connected to the conversion trigger pin, and this GPIO is controlled 93 by the driver directly. In this configuration, the driver sets back the 94 conversion trigger pin to high as soon as it has read all the conversions. 95 96 - An external source is connected to the conversion trigger pin. In the 97 current implementation, it must be a PWM. In this configuration, the driver 98 does not control directly the conversion trigger pin. Instead, it can 99 control the PWM's frequency. This trigger is enabled only for iio-backend. 100 101Reference voltage 102----------------- 103 1042 possible reference voltage sources are supported: 105 106 - Internal reference (2.5V) 107 - External reference (2.5V) 108 109The source is determined by the device tree. If ``refin-supply`` is present, 110then the external reference is used, otherwise the internal reference is used. 111 112Oversampling 113------------ 114 115This family supports oversampling to improve SNR. 116In software mode, the following ratios are available: 1171 (oversampling disabled)/2/4/8/16/32/64/128/256. 118 119Unimplemented features 120---------------------- 121 122- 2/4/8 SDO lines 123- CRC indication 124- Calibration 125 126Device buffers 127============== 128 129IIO triggered buffer 130-------------------- 131 132This driver supports IIO triggered buffers, with a "built in" trigger, i.e the 133trigger is allocated and linked by the driver, and a new conversion is triggered 134as soon as the samples are transferred, and a timestamp channel is added to make 135up for the potential jitter induced by the delays in the interrupt handling. 136 137IIO backend buffer 138------------------ 139 140When IIO backend is used, the trigger is not needed, and the sample rate is 141considered as stable. There is no timestamp channel. The communication is 142delegated to an external logic, called a backend, and the backend's driver 143handles the buffer. When this mode is enabled, the driver cannot control the 144conversion pin, because the busy pin is bound to the backend. 145