1.. SPDX-License-Identifier: GPL-2.0-only 2 3============= 4AD4030 driver 5============= 6 7ADC driver for Analog Devices Inc. AD4030 and similar devices. The module name 8is ``ad4030``. 9 10 11Supported devices 12================= 13 14The following chips are supported by this driver: 15 16* `AD4030-24 <https://www.analog.com/AD4030-24>`_ 17* `AD4032-24 <https://www.analog.com/AD4032-24>`_ 18* `AD4630-16 <https://www.analog.com/AD4630-16>`_ 19* `AD4630-24 <https://www.analog.com/AD4630-24>`_ 20* `AD4632-16 <https://www.analog.com/AD4632-16>`_ 21* `AD4632-24 <https://www.analog.com/AD4632-24>`_ 22 23IIO channels 24============ 25 26Each "hardware" channel as described in the datasheet is split in 2 IIO 27channels: 28 29- One channel for the differential data 30- One channel for the common byte. 31 32The possible IIO channels depending on the numbers of "hardware" channel are: 33 34+------------------------------------+------------------------------------+ 35| 1 channel ADC | 2 channels ADC | 36+====================================+====================================+ 37| - voltage0-voltage1 (differential) | - voltage0-voltage1 (differential) | 38| - voltage2 (common-mode) | - voltage2-voltage3 (differential) | 39| | - voltage4 (common-mode) | 40| | - voltage5 (common-mode) | 41+------------------------------------+------------------------------------+ 42 43Labels 44------ 45 46For ease of use, the IIO channels provide a label. For a differential channel, 47the label is ``differentialN`` where ``N`` is the "hardware" channel id. For a 48common-mode channel, the label is ``common-modeN`` where ``N`` is the 49"hardware" channel id. 50 51The possible labels are: 52 53+-----------------+-----------------+ 54| 1 channel ADC | 2 channels ADC | 55+=================+=================+ 56| - differential0 | - differential0 | 57| - common-mode0 | - differential1 | 58| | - common-mode0 | 59| | - common-mode1 | 60+-----------------+-----------------+ 61 62Supported features 63================== 64 65SPI wiring modes 66---------------- 67 68The driver currently supports the following SPI wiring configurations: 69 70One lane mode 71^^^^^^^^^^^^^ 72 73In this mode, each channel has its own SDO line to send the conversion results. 74At the moment this mode can only be used on AD4030 which has one channel so only 75one SDO line is used. 76 77.. code-block:: 78 79 +-------------+ +-------------+ 80 | ADC | | HOST | 81 | | | | 82 | CNV |<--------| CNV | 83 | CS |<--------| CS | 84 | SDI |<--------| SDO | 85 | SDO0 |-------->| SDI | 86 | SCLK |<--------| SCLK | 87 +-------------+ +-------------+ 88 89Interleaved mode 90^^^^^^^^^^^^^^^^ 91 92In this mode, both channels conversion results are bit interleaved one SDO line. 93As such the wiring is the same as `One lane mode`_. 94 95SPI offload wiring 96^^^^^^^^^^^^^^^^^^ 97 98.. code-block:: 99 100 +-------------+ +-------------+ 101 | CNV |<-----+--| GPIO | 102 | | +--| PWM0 | 103 | | | | 104 | | +--| PWM1 | 105 | | | +-------------+ 106 | | +->| TRIGGER | 107 | CS |<--------| CS | 108 | | | | 109 | ADC | | SPI | 110 | | | | 111 | SDI |<--------| SDO | 112 | SDO |-------->| SDI | 113 | SCLK |<--------| SCLK | 114 +-------------+ +-------------+ 115 116In this mode, both the ``cnv-gpios`` and a ``pwms`` properties are required. 117The ``pwms`` property specifies the PWM that is connected to the ADC CNV pin. 118The SPI offload will have a ``trigger-sources`` property to indicate the SPI 119offload (PWM) trigger source. For AD4030 and similar ADCs, there are two 120possible data transfer zones for sample N. One of them (zone 1) starts after the 121data conversion for sample N is complete while the other one (zone 2) starts 9.8 122nanoseconds after the rising edge of CNV for sample N + 1. 123 124The configuration depicted in the above diagram is intended to perform data 125transfer in zone 2. To achieve high sample rates while meeting ADC timing 126requirements, an offset is added between the rising edges of PWM0 and PWM1 to 127delay the SPI transfer until 9.8 nanoseconds after CNV rising edge. This 128requires a specialized PWM controller that can provide such an offset. 129The `AD4630-FMC HDL project`_, for example, can be configured to sample AD4030 130data during zone 2 data read window. 131 132.. _AD4630-FMC HDL project: https://analogdevicesinc.github.io/hdl/projects/ad4630_fmc/index.html 133 134SPI Clock mode 135-------------- 136 137Only the SPI clocking mode is supported. 138 139Output modes 140------------ 141 142There are more exposed IIO channels than channels as describe in the devices 143datasheet. This is due to the `Differential data + common-mode`_ encoding 1442 types of information in one conversion result. As such a "device" channel 145provides 2 IIO channels, one for the differential data and one for the common 146byte. 147 148Differential data 149^^^^^^^^^^^^^^^^^ 150 151This mode is selected when: 152 153- Only differential channels are enabled in a buffered read 154- Oversampling attribute is set to 1 155 156Differential data + common-mode 157^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ 158 159This mode is selected when: 160 161- Differential and common-mode channels are enabled in a buffered read 162- Oversampling attribute is set to 1 163 164For the 24-bits chips, this mode is also available with 16-bits differential 165data but is not selectable yet. 166 167Averaged differential data 168^^^^^^^^^^^^^^^^^^^^^^^^^^ 169 170This mode is selected when: 171 172- Only differential channels are selected enabled in a buffered read 173- Oversampling attribute is greater than 1 174 175Digital Gain and Offset 176----------------------- 177 178Each differential data channel has a 16-bits unsigned configurable hardware 179gain applied to it. By default it's equal to 1. Note that applying gain can 180cause numerical saturation. 181 182Each differential data channel has a signed configurable hardware offset. 183For the ADCs ending in ``-24``, the gain is encoded on 24-bits. 184Likewise, the ADCs ending in ``-16`` have a gain encoded on 16-bits. Note that 185applying an offset can cause numerical saturation. 186 187The final differential data returned by the ADC is computed by first applying 188the gain, then the offset. 189 190The gain is controlled by the ``calibscale`` IIO attribute while the offset is 191controlled by the ``calibbias`` attribute. 192 193Reference voltage 194----------------- 195 196The chip supports an external reference voltage via the ``REF`` input or an 197internal buffered reference voltage via the ``REFIN`` input. The driver looks 198at the device tree to determine which is being used. If ``ref-supply`` is 199present, then the external reference voltage is used and the internal buffer is 200disabled. If ``refin-supply`` is present, then the internal buffered reference 201voltage is used. 202 203Reset 204----- 205 206Both hardware and software reset are supported. The driver looks first at the 207device tree to see if the ``reset-gpio`` is populated. 208If not present, the driver will fallback to a software reset by wiring to the 209device's registers. 210 211Unimplemented features 212---------------------- 213 214- ``BUSY`` indication 215- Additional wiring modes 216- Additional clock modes 217- Differential data 16-bits + common-mode for 24-bits chips 218- Overrange events 219- Test patterns 220