1*a3a2923aSWensheng Wang.. SPDX-License-Identifier: GPL-2.0 2*a3a2923aSWensheng Wang 3*a3a2923aSWensheng WangKernel driver mp2869 4*a3a2923aSWensheng Wang==================== 5*a3a2923aSWensheng Wang 6*a3a2923aSWensheng WangSupported chips: 7*a3a2923aSWensheng Wang 8*a3a2923aSWensheng Wang * MPS mp2869 9*a3a2923aSWensheng Wang 10*a3a2923aSWensheng Wang Prefix: 'mp2869' 11*a3a2923aSWensheng Wang 12*a3a2923aSWensheng Wang * MPS mp29608 13*a3a2923aSWensheng Wang 14*a3a2923aSWensheng Wang Prefix: 'mp29608' 15*a3a2923aSWensheng Wang 16*a3a2923aSWensheng Wang * MPS mp29612 17*a3a2923aSWensheng Wang 18*a3a2923aSWensheng Wang Prefix: 'mp29612' 19*a3a2923aSWensheng Wang 20*a3a2923aSWensheng Wang * MPS mp29816 21*a3a2923aSWensheng Wang 22*a3a2923aSWensheng Wang Prefix: 'mp29816' 23*a3a2923aSWensheng Wang 24*a3a2923aSWensheng WangAuthor: 25*a3a2923aSWensheng Wang 26*a3a2923aSWensheng Wang Wensheng Wang <wenswang@yeah.net> 27*a3a2923aSWensheng Wang 28*a3a2923aSWensheng WangDescription 29*a3a2923aSWensheng Wang----------- 30*a3a2923aSWensheng Wang 31*a3a2923aSWensheng WangThis driver implements support for Monolithic Power Systems, Inc. (MPS) 32*a3a2923aSWensheng WangMP2869 Dual Loop Digital Multi-phase Controller. 33*a3a2923aSWensheng Wang 34*a3a2923aSWensheng WangDevice compliant with: 35*a3a2923aSWensheng Wang 36*a3a2923aSWensheng Wang- PMBus rev 1.3 interface. 37*a3a2923aSWensheng Wang 38*a3a2923aSWensheng WangThe driver exports the following attributes via the 'sysfs' files 39*a3a2923aSWensheng Wangfor input voltage: 40*a3a2923aSWensheng Wang 41*a3a2923aSWensheng Wang**in1_input** 42*a3a2923aSWensheng Wang 43*a3a2923aSWensheng Wang**in1_label** 44*a3a2923aSWensheng Wang 45*a3a2923aSWensheng Wang**in1_crit** 46*a3a2923aSWensheng Wang 47*a3a2923aSWensheng Wang**in1_crit_alarm** 48*a3a2923aSWensheng Wang 49*a3a2923aSWensheng Wang**in1_lcrit** 50*a3a2923aSWensheng Wang 51*a3a2923aSWensheng Wang**in1_lcrit_alarm** 52*a3a2923aSWensheng Wang 53*a3a2923aSWensheng Wang**in1_min** 54*a3a2923aSWensheng Wang 55*a3a2923aSWensheng Wang**in1_min_alarm** 56*a3a2923aSWensheng Wang 57*a3a2923aSWensheng WangThe driver provides the following attributes for output voltage: 58*a3a2923aSWensheng Wang 59*a3a2923aSWensheng Wang**in2_input** 60*a3a2923aSWensheng Wang 61*a3a2923aSWensheng Wang**in2_label** 62*a3a2923aSWensheng Wang 63*a3a2923aSWensheng Wang**in2_crit** 64*a3a2923aSWensheng Wang 65*a3a2923aSWensheng Wang**in2_crit_alarm** 66*a3a2923aSWensheng Wang 67*a3a2923aSWensheng Wang**in2_lcrit** 68*a3a2923aSWensheng Wang 69*a3a2923aSWensheng Wang**in2_lcrit_alarm** 70*a3a2923aSWensheng Wang 71*a3a2923aSWensheng Wang**in3_input** 72*a3a2923aSWensheng Wang 73*a3a2923aSWensheng Wang**in3_label** 74*a3a2923aSWensheng Wang 75*a3a2923aSWensheng Wang**in3_crit** 76*a3a2923aSWensheng Wang 77*a3a2923aSWensheng Wang**in3_crit_alarm** 78*a3a2923aSWensheng Wang 79*a3a2923aSWensheng Wang**in3_lcrit** 80*a3a2923aSWensheng Wang 81*a3a2923aSWensheng Wang**in3_lcrit_alarm** 82*a3a2923aSWensheng Wang 83*a3a2923aSWensheng WangThe driver provides the following attributes for input current: 84*a3a2923aSWensheng Wang 85*a3a2923aSWensheng Wang**curr1_input** 86*a3a2923aSWensheng Wang 87*a3a2923aSWensheng Wang**curr1_label** 88*a3a2923aSWensheng Wang 89*a3a2923aSWensheng Wang**curr2_input** 90*a3a2923aSWensheng Wang 91*a3a2923aSWensheng Wang**curr2_label** 92*a3a2923aSWensheng Wang 93*a3a2923aSWensheng WangThe driver provides the following attributes for output current: 94*a3a2923aSWensheng Wang 95*a3a2923aSWensheng Wang**curr3_input** 96*a3a2923aSWensheng Wang 97*a3a2923aSWensheng Wang**curr3_label** 98*a3a2923aSWensheng Wang 99*a3a2923aSWensheng Wang**curr3_crit** 100*a3a2923aSWensheng Wang 101*a3a2923aSWensheng Wang**curr3_crit_alarm** 102*a3a2923aSWensheng Wang 103*a3a2923aSWensheng Wang**curr3_max** 104*a3a2923aSWensheng Wang 105*a3a2923aSWensheng Wang**curr3_max_alarm** 106*a3a2923aSWensheng Wang 107*a3a2923aSWensheng Wang**curr4_input** 108*a3a2923aSWensheng Wang 109*a3a2923aSWensheng Wang**curr4_label** 110*a3a2923aSWensheng Wang 111*a3a2923aSWensheng Wang**curr4_crit** 112*a3a2923aSWensheng Wang 113*a3a2923aSWensheng Wang**curr4_crit_alarm** 114*a3a2923aSWensheng Wang 115*a3a2923aSWensheng Wang**curr4_max** 116*a3a2923aSWensheng Wang 117*a3a2923aSWensheng Wang**curr4_max_alarm** 118*a3a2923aSWensheng Wang 119*a3a2923aSWensheng WangThe driver provides the following attributes for input power: 120*a3a2923aSWensheng Wang 121*a3a2923aSWensheng Wang**power1_input** 122*a3a2923aSWensheng Wang 123*a3a2923aSWensheng Wang**power1_label** 124*a3a2923aSWensheng Wang 125*a3a2923aSWensheng Wang**power2_input** 126*a3a2923aSWensheng Wang 127*a3a2923aSWensheng Wang**power2_label** 128*a3a2923aSWensheng Wang 129*a3a2923aSWensheng WangThe driver provides the following attributes for output power: 130*a3a2923aSWensheng Wang 131*a3a2923aSWensheng Wang**power3_input** 132*a3a2923aSWensheng Wang 133*a3a2923aSWensheng Wang**power3_label** 134*a3a2923aSWensheng Wang 135*a3a2923aSWensheng Wang**power3_input** 136*a3a2923aSWensheng Wang 137*a3a2923aSWensheng Wang**power3_label** 138*a3a2923aSWensheng Wang 139*a3a2923aSWensheng Wang**power3_max** 140*a3a2923aSWensheng Wang 141*a3a2923aSWensheng Wang**power3_max_alarm** 142*a3a2923aSWensheng Wang 143*a3a2923aSWensheng Wang**power4_input** 144*a3a2923aSWensheng Wang 145*a3a2923aSWensheng Wang**power4_label** 146*a3a2923aSWensheng Wang 147*a3a2923aSWensheng Wang**power4_input** 148*a3a2923aSWensheng Wang 149*a3a2923aSWensheng Wang**power4_label** 150*a3a2923aSWensheng Wang 151*a3a2923aSWensheng Wang**power4_max** 152*a3a2923aSWensheng Wang 153*a3a2923aSWensheng Wang**power4_max_alarm** 154*a3a2923aSWensheng Wang 155*a3a2923aSWensheng WangThe driver provides the following attributes for temperature: 156*a3a2923aSWensheng Wang 157*a3a2923aSWensheng Wang**temp1_input** 158*a3a2923aSWensheng Wang 159*a3a2923aSWensheng Wang**temp1_crit** 160*a3a2923aSWensheng Wang 161*a3a2923aSWensheng Wang**temp1_crit_alarm** 162*a3a2923aSWensheng Wang 163*a3a2923aSWensheng Wang**temp1_max** 164*a3a2923aSWensheng Wang 165*a3a2923aSWensheng Wang**temp1_max_alarm** 166*a3a2923aSWensheng Wang 167*a3a2923aSWensheng Wang**temp2_input** 168*a3a2923aSWensheng Wang 169*a3a2923aSWensheng Wang**temp2_crit** 170*a3a2923aSWensheng Wang 171*a3a2923aSWensheng Wang**temp2_crit_alarm** 172*a3a2923aSWensheng Wang 173*a3a2923aSWensheng Wang**temp2_max** 174*a3a2923aSWensheng Wang 175*a3a2923aSWensheng Wang**temp2_max_alarm** 176