1.. SPDX-License-Identifier: GPL-2.0 2 3Kernel driver max16601 4====================== 5 6Supported chips: 7 8 * Maxim MAX16508 9 10 Prefix: 'max16508' 11 12 Addresses scanned: - 13 14 Datasheet: Not published 15 16 * Maxim MAX16601 17 18 Prefix: 'max16601' 19 20 Addresses scanned: - 21 22 Datasheet: Not published 23 24 * Maxim MAX16602 25 26 Prefix: 'max16602' 27 28 Addresses scanned: - 29 30 Datasheet: https://datasheets.maximintegrated.com/en/ds/MAX16602.pdf 31 32Author: Guenter Roeck <linux@roeck-us.net> 33 34 35Description 36----------- 37 38This driver supports the MAX16508 VR13 Dual-Output Voltage Regulator 39as well as the MAX16601 VR13.HC Dual-Output Voltage Regulator chipsets. 40 41The driver is a client driver to the core PMBus driver. 42Please see Documentation/hwmon/pmbus.rst for details on PMBus client drivers. 43 44 45Usage Notes 46----------- 47 48This driver does not auto-detect devices. You will have to instantiate the 49devices explicitly. Please see Documentation/i2c/instantiating-devices.rst for 50details. 51 52 53Platform data support 54--------------------- 55 56The driver supports standard PMBus driver platform data. 57 58 59Sysfs entries 60------------- 61 62The following attributes are supported. 63 64=============================== =============================================== 65in1_label "vin1" 66in1_input VCORE input voltage. 67in1_alarm Input voltage alarm. 68 69in2_label "vout1" 70in2_input VCORE output voltage. 71in2_alarm Output voltage alarm. 72 73curr1_label "iin1" 74curr1_input VCORE input current, derived from duty cycle 75 and output current. 76curr1_max Maximum input current. 77curr1_max_alarm Current high alarm. 78 79curr[P+2]_label "iin1.P" 80curr[P+2]_input VCORE phase P input current. 81 82curr[N+2]_label "iin2" 83curr[N+2]_input VCORE input current, derived from sensor 84 element. 85 'N' is the number of enabled/populated phases. 86 87curr[N+3]_label "iin3" 88curr[N+3]_input VSA input current. 89 90curr[N+4]_label "iout1" 91curr[N+4]_input VCORE output current. 92curr[N+4]_crit Critical output current. 93curr[N+4]_crit_alarm Output current critical alarm. 94curr[N+4]_max Maximum output current. 95curr[N+4]_max_alarm Output current high alarm. 96 97curr[N+P+5]_label "iout1.P" 98curr[N+P+5]_input VCORE phase P output current. 99 100curr[2*N+5]_label "iout3" 101curr[2*N+5]_input VSA output current. 102curr[2*N+5]_highest Historical maximum VSA output current. 103curr[2*N+5]_reset_history Write any value to reset curr21_highest. 104curr[2*N+5]_crit Critical output current. 105curr[2*N+5]_crit_alarm Output current critical alarm. 106curr[2*N+5]_max Maximum output current. 107curr[2*N+5]_max_alarm Output current high alarm. 108 109power1_label "pin1" 110power1_input Input power, derived from duty cycle and output 111 current. 112power1_alarm Input power alarm. 113 114power2_label "pin2" 115power2_input Input power, derived from input current sensor. 116 117power3_label "pout" 118power3_input Output power. 119 120temp1_input VCORE temperature. 121temp1_crit Critical high temperature. 122temp1_crit_alarm Chip temperature critical high alarm. 123temp1_max Maximum temperature. 124temp1_max_alarm Chip temperature high alarm. 125 126temp2_input TSENSE_0 temperature 127temp3_input TSENSE_1 temperature 128temp4_input TSENSE_2 temperature 129temp5_input TSENSE_3 temperature 130 131temp6_input VSA temperature. 132temp6_crit Critical high temperature. 133temp6_crit_alarm Chip temperature critical high alarm. 134temp6_max Maximum temperature. 135temp6_max_alarm Chip temperature high alarm. 136=============================== =============================================== 137