1=========================== 2 drm/i915 Intel GFX Driver 3=========================== 4 5The drm/i915 driver supports all (with the exception of some very early 6models) integrated GFX chipsets with both Intel display and rendering 7blocks. This excludes a set of SoC platforms with an SGX rendering unit, 8those have basic support through the gma500 drm driver. 9 10Core Driver Infrastructure 11========================== 12 13This section covers core driver infrastructure used by both the display 14and the GEM parts of the driver. 15 16Runtime Power Management 17------------------------ 18 19.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 20 :doc: runtime pm 21 22.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 23 :internal: 24 25.. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c 26 :internal: 27 28Interrupt Handling 29------------------ 30 31.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 32 :doc: interrupt handling 33 34.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 35 :functions: intel_irq_init intel_irq_init_hw intel_hpd_init 36 37.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 38 :functions: intel_irq_suspend 39 40.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 41 :functions: intel_irq_resume 42 43Intel GVT-g Guest Support(vGPU) 44------------------------------- 45 46.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 47 :doc: Intel GVT-g guest support 48 49.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 50 :internal: 51 52Intel GVT-g Host Support(vGPU device model) 53------------------------------------------- 54 55.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 56 :doc: Intel GVT-g host support 57 58.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 59 :internal: 60 61Workarounds 62----------- 63 64.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c 65 :doc: Hardware workarounds 66 67Display Hardware Handling 68========================= 69 70This section covers everything related to the display hardware including 71the mode setting infrastructure, plane, sprite and cursor handling and 72display, output probing and related topics. 73 74Mode Setting Infrastructure 75--------------------------- 76 77The i915 driver is thus far the only DRM driver which doesn't use the 78common DRM helper code to implement mode setting sequences. Thus it has 79its own tailor-made infrastructure for executing a display configuration 80change. 81 82Frontbuffer Tracking 83-------------------- 84 85.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 86 :doc: frontbuffer tracking 87 88.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h 89 :internal: 90 91.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 92 :internal: 93 94Display FIFO Underrun Reporting 95------------------------------- 96 97.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 98 :doc: fifo underrun handling 99 100.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 101 :internal: 102 103Plane Configuration 104------------------- 105 106This section covers plane configuration and composition with the primary 107plane, sprites, cursors and overlays. This includes the infrastructure 108to do atomic vsync'ed updates of all this state and also tightly coupled 109topics like watermark setup and computation, framebuffer compression and 110panel self refresh. 111 112Atomic Plane Helpers 113-------------------- 114 115.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c 116 :doc: atomic plane helpers 117 118.. kernel-doc:: drivers/gpu/drm/i915/display/intel_plane.c 119 :internal: 120 121Asynchronous Page Flip 122---------------------- 123 124.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c 125 :doc: asynchronous flip implementation 126 127Output Probing 128-------------- 129 130This section covers output probing and related infrastructure like the 131hotplug interrupt storm detection and mitigation code. Note that the 132i915 driver still uses most of the common DRM helper code for output 133probing, so those sections fully apply. 134 135Hotplug 136------- 137 138.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 139 :doc: Hotplug 140 141.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 142 :internal: 143 144High Definition Audio 145--------------------- 146 147.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 148 :doc: High Definition Audio over HDMI and Display Port 149 150.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 151 :internal: 152 153.. kernel-doc:: include/drm/intel/i915_component.h 154 :internal: 155 156Intel HDMI LPE Audio Support 157---------------------------- 158 159.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 160 :doc: LPE Audio integration for HDMI or DP playback 161 162.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 163 :internal: 164 165Panel Self Refresh PSR (PSR/SRD) 166-------------------------------- 167 168.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 169 :doc: Panel Self Refresh (PSR/SRD) 170 171.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 172 :internal: 173 174Frame Buffer Compression (FBC) 175------------------------------ 176 177.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 178 :doc: Frame Buffer Compression (FBC) 179 180.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 181 :internal: 182 183Display Refresh Rate Switching (DRRS) 184------------------------------------- 185 186.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 187 :doc: Display Refresh Rate Switching (DRRS) 188 189.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 190 :internal: 191 192DPIO 193---- 194 195.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c 196 :doc: DPIO 197 198DMC Firmware Support 199-------------------- 200 201.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c 202 :doc: DMC Firmware Support 203 204.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c 205 :internal: 206 207DMC Flip Queue 208-------------------- 209 210.. kernel-doc:: drivers/gpu/drm/i915/display/intel_flipq.c 211 :doc: DMC Flip Queue 212 213DMC wakelock support 214-------------------- 215 216.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc_wl.c 217 :doc: DMC wakelock support 218 219Video BIOS Table (VBT) 220---------------------- 221 222.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 223 :doc: Video BIOS Table (VBT) 224 225.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 226 :internal: 227 228.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h 229 :internal: 230 231Display clocks 232-------------- 233 234.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 235 :doc: CDCLK / RAWCLK 236 237.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 238 :internal: 239 240Display PLLs 241------------ 242 243.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 244 :doc: Display PLLs 245 246.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 247 :internal: 248 249.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h 250 :internal: 251 252Display State Buffer 253-------------------- 254 255.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 256 :doc: DSB 257 258.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 259 :internal: 260 261GT Programming 262============== 263 264Multicast/Replicated (MCR) Registers 265------------------------------------ 266 267.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c 268 :doc: GT Multicast/Replicated (MCR) Register Support 269 270.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_gt_mcr.c 271 :internal: 272 273Memory Management and Command Submission 274======================================== 275 276This sections covers all things related to the GEM implementation in the 277i915 driver. 278 279Intel GPU Basics 280---------------- 281 282An Intel GPU has multiple engines. There are several engine types: 283 284- Render Command Streamer (RCS). An engine for rendering 3D and 285 performing compute. 286- Blitting Command Streamer (BCS). An engine for performing blitting and/or 287 copying operations. 288- Video Command Streamer. An engine used for video encoding and decoding. Also 289 sometimes called 'BSD' in hardware documentation. 290- Video Enhancement Command Streamer (VECS). An engine for video enhancement. 291 Also sometimes called 'VEBOX' in hardware documentation. 292- Compute Command Streamer (CCS). An engine that has access to the media and 293 GPGPU pipelines, but not the 3D pipeline. 294- Graphics Security Controller (GSCCS). A dedicated engine for internal 295 communication with GSC controller on security related tasks like 296 High-bandwidth Digital Content Protection (HDCP), Protected Xe Path (PXP), 297 and HuC firmware authentication. 298 299The Intel GPU family is a family of integrated GPU's using Unified 300Memory Access. For having the GPU "do work", user space will feed the 301GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` 302or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will 303instruct the GPU to perform work (for example rendering) and that work 304needs memory from which to read and memory to which to write. All memory 305is encapsulated within GEM buffer objects (usually created with the ioctl 306`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU 307to create will also list all GEM buffer objects that the batchbuffer reads 308and/or writes. For implementation details of memory management see 309`GEM BO Management Implementation Details`_. 310 311The i915 driver allows user space to create a context via the ioctl 312`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit 313integer. Such a context should be viewed by user-space as -loosely- 314analogous to the idea of a CPU process of an operating system. The i915 315driver guarantees that commands issued to a fixed context are to be 316executed so that writes of a previously issued command are seen by 317reads of following commands. Actions issued between different contexts 318(even if from the same file descriptor) are NOT given that guarantee 319and the only way to synchronize across contexts (even from the same 320file descriptor) is through the use of fences. At least as far back as 321Gen4, also have that a context carries with it a GPU HW context; 322the HW context is essentially (most of at least) the state of a GPU. 323In addition to the ordering guarantees, the kernel will restore GPU 324state via HW context when commands are issued to a context, this saves 325user space the need to restore (most of at least) the GPU state at the 326start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer 327work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) 328to identify what context to use with the command. 329 330The GPU has its own memory management and address space. The kernel 331driver maintains the memory translation table for the GPU. For older 332GPUs (i.e. those before Gen8), there is a single global such translation 333table, a global Graphics Translation Table (GTT). For newer generation 334GPUs each context has its own translation table, called Per-Process 335Graphics Translation Table (PPGTT). Of important note, is that although 336PPGTT is named per-process it is actually per context. When user space 337submits a batchbuffer, the kernel walks the list of GEM buffer objects 338used by the batchbuffer and guarantees that not only is the memory of 339each such GEM buffer object resident but it is also present in the 340(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, 341then it is given an address. Two consequences of this are: the kernel 342needs to edit the batchbuffer submitted to write the correct value of 343the GPU address when a GEM BO is assigned a GPU address and the kernel 344might evict a different GEM BO from the (PP)GTT to make address room 345for another GEM BO. Consequently, the ioctls submitting a batchbuffer 346for execution also include a list of all locations within buffers that 347refer to GPU-addresses so that the kernel can edit the buffer correctly. 348This process is dubbed relocation. 349 350Locking Guidelines 351------------------ 352 353.. note:: 354 This is a description of how the locking should be after 355 refactoring is done. Does not necessarily reflect what the locking 356 looks like while WIP. 357 358#. All locking rules and interface contracts with cross-driver interfaces 359 (dma-buf, dma_fence) need to be followed. 360 361#. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx 362 is to be hoisted at highest level and passed down within i915_gem_ctx 363 in the call chain 364 365#. While holding lru/memory manager (buddy, drm_mm, whatever) locks 366 system memory allocations are not allowed 367 368#. Do not nest different lru/memory manager locks within each other. 369 Take them in turn to update memory allocations, relying on the object’s 370 dma_resv ww_mutex to serialize against other operations. 371 372#. The suggestion for lru/memory managers locks is that they are small 373 enough to be spinlocks. 374 375#. All features need to come with exhaustive kernel selftests and/or 376 IGT tests when appropriate 377 378#. All LMEM uAPI paths need to be fully restartable (_interruptible() 379 for all locks/waits/sleeps) 380 381 * Error handling validation through signal injection. 382 Still the best strategy we have for validating GEM uAPI 383 corner cases. 384 Must be excessively used in the IGT, and we need to check 385 that we really have full path coverage of all error cases. 386 387 * -EDEADLK handling with ww_mutex 388 389GEM BO Management Implementation Details 390---------------------------------------- 391 392.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 393 :doc: Virtual Memory Address 394 395Buffer Object Eviction 396---------------------- 397 398This section documents the interface functions for evicting buffer 399objects to make space available in the virtual gpu address spaces. Note 400that this is mostly orthogonal to shrinking buffer objects caches, which 401has the goal to make main memory (shared with the gpu through the 402unified memory architecture) available. 403 404.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c 405 :internal: 406 407Buffer Object Memory Shrinking 408------------------------------ 409 410This section documents the interface function for shrinking memory usage 411of buffer object caches. Shrinking is used to make main memory 412available. Note that this is mostly orthogonal to evicting buffer 413objects, which has the goal to make space in gpu virtual address spaces. 414 415.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 416 :internal: 417 418Batchbuffer Parsing 419------------------- 420 421.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 422 :doc: batch buffer command parser 423 424.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 425 :internal: 426 427User Batchbuffer Execution 428-------------------------- 429 430.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_context_types.h 431 432.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 433 :doc: User command execution 434 435Scheduling 436---------- 437.. kernel-doc:: drivers/gpu/drm/i915/i915_scheduler_types.h 438 :functions: i915_sched_engine 439 440Logical Rings, Logical Ring Contexts and Execlists 441-------------------------------------------------- 442 443.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_execlists_submission.c 444 :doc: Logical Rings, Logical Ring Contexts and Execlists 445 446Global GTT views 447---------------- 448 449.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 450 :doc: Global GTT views 451 452.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c 453 :internal: 454 455GTT Fences and Swizzling 456------------------------ 457 458.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 459 :internal: 460 461Global GTT Fence Handling 462~~~~~~~~~~~~~~~~~~~~~~~~~ 463 464.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 465 :doc: fence register handling 466 467Hardware Tiling and Swizzling Details 468~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 469 470.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 471 :doc: tiling swizzling details 472 473Object Tiling IOCTLs 474-------------------- 475 476.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 477 :internal: 478 479.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 480 :doc: buffer object tiling 481 482Protected Objects 483----------------- 484 485.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp.c 486 :doc: PXP 487 488.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp_types.h 489 490Microcontrollers 491================ 492 493Starting from gen9, three microcontrollers are available on the HW: the 494graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the 495display microcontroller (DMC). The driver is responsible for loading the 496firmwares on the microcontrollers; the GuC and HuC firmwares are transferred 497to WOPCM using the DMA engine, while the DMC firmware is written through MMIO. 498 499WOPCM 500----- 501 502WOPCM Layout 503~~~~~~~~~~~~ 504 505.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_wopcm.c 506 :doc: WOPCM Layout 507 508GuC 509--- 510 511.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 512 :doc: GuC 513 514.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.h 515 516GuC Firmware Layout 517~~~~~~~~~~~~~~~~~~~ 518 519.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 520 :doc: Firmware Layout 521 522GuC Memory Management 523~~~~~~~~~~~~~~~~~~~~~ 524 525.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 526 :doc: GuC Memory Management 527.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 528 :functions: intel_guc_allocate_vma 529 530 531GuC-specific firmware loader 532~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 533 534.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 535 :internal: 536 537GuC-based command submission 538~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 539 540.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 541 :doc: GuC-based command submission 542 543GuC ABI 544~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 545 546.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h 547.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h 548.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h 549.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 550.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h 551 552HuC 553--- 554.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 555 :doc: HuC 556.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 557 :functions: intel_huc_auth 558 559HuC Memory Management 560~~~~~~~~~~~~~~~~~~~~~ 561 562.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 563 :doc: HuC Memory Management 564 565HuC Firmware Layout 566~~~~~~~~~~~~~~~~~~~ 567The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_ 568 569DMC 570--- 571See `DMC Firmware Support`_ 572 573Tracing 574======= 575 576This sections covers all things related to the tracepoints implemented 577in the i915 driver. 578 579i915_ppgtt_create and i915_ppgtt_release 580---------------------------------------- 581 582.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 583 :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints 584 585i915_context_create and i915_context_free 586----------------------------------------- 587 588.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 589 :doc: i915_context_create and i915_context_free tracepoints 590 591Perf 592==== 593 594Overview 595-------- 596.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 597 :doc: i915 Perf Overview 598 599Comparison with Core Perf 600------------------------- 601.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 602 :doc: i915 Perf History and Comparison with Core Perf 603 604i915 Driver Entry Points 605------------------------ 606 607This section covers the entrypoints exported outside of i915_perf.c to 608integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl. 609 610.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 611 :functions: i915_perf_init 612.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 613 :functions: i915_perf_fini 614.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 615 :functions: i915_perf_register 616.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 617 :functions: i915_perf_unregister 618.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 619 :functions: i915_perf_open_ioctl 620.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 621 :functions: i915_perf_release 622.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 623 :functions: i915_perf_add_config_ioctl 624.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 625 :functions: i915_perf_remove_config_ioctl 626 627i915 Perf Stream 628---------------- 629 630This section covers the stream-semantics-agnostic structures and functions 631for representing an i915 perf stream FD and associated file operations. 632 633.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 634 :functions: i915_perf_stream 635.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 636 :functions: i915_perf_stream_ops 637 638.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 639 :functions: read_properties_unlocked 640.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 641 :functions: i915_perf_open_ioctl_locked 642.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 643 :functions: i915_perf_destroy_locked 644.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 645 :functions: i915_perf_read 646.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 647 :functions: i915_perf_ioctl 648.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 649 :functions: i915_perf_enable_locked 650.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 651 :functions: i915_perf_disable_locked 652.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 653 :functions: i915_perf_poll 654.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 655 :functions: i915_perf_poll_locked 656 657i915 Perf Observation Architecture Stream 658----------------------------------------- 659 660.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 661 :functions: i915_oa_ops 662 663.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 664 :functions: i915_oa_stream_init 665.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 666 :functions: i915_oa_read 667.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 668 :functions: i915_oa_stream_enable 669.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 670 :functions: i915_oa_stream_disable 671.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 672 :functions: i915_oa_wait_unlocked 673.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 674 :functions: i915_oa_poll_wait 675 676Other i915 Perf Internals 677------------------------- 678 679This section simply includes all other currently documented i915 perf internals, 680in no particular order, but may include some more minor utilities or platform 681specific details than found in the more high-level sections. 682 683.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 684 :internal: 685 :no-identifiers: 686 i915_perf_init 687 i915_perf_fini 688 i915_perf_register 689 i915_perf_unregister 690 i915_perf_open_ioctl 691 i915_perf_release 692 i915_perf_add_config_ioctl 693 i915_perf_remove_config_ioctl 694 read_properties_unlocked 695 i915_perf_open_ioctl_locked 696 i915_perf_destroy_locked 697 i915_perf_read i915_perf_ioctl 698 i915_perf_enable_locked 699 i915_perf_disable_locked 700 i915_perf_poll i915_perf_poll_locked 701 i915_oa_stream_init i915_oa_read 702 i915_oa_stream_enable 703 i915_oa_stream_disable 704 i915_oa_wait_unlocked 705 i915_oa_poll_wait 706 707Style 708===== 709 710The drm/i915 driver codebase has some style rules in addition to (and, in some 711cases, deviating from) the kernel coding style. 712 713Register macro definition style 714------------------------------- 715 716The style guide for ``i915_reg.h``. 717 718.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h 719 :doc: The i915 register macro definition style guide 720 721.. _i915-usage-stats: 722 723i915 DRM client usage stats implementation 724========================================== 725 726The drm/i915 driver implements the DRM client usage stats specification as 727documented in :ref:`drm-client-usage-stats`. 728 729Example of the output showing the implemented key value pairs and entirety of 730the currently possible format options: 731 732:: 733 734 pos: 0 735 flags: 0100002 736 mnt_id: 21 737 drm-driver: i915 738 drm-pdev: 0000:00:02.0 739 drm-client-id: 7 740 drm-engine-render: 9288864723 ns 741 drm-engine-copy: 2035071108 ns 742 drm-engine-video: 0 ns 743 drm-engine-capacity-video: 2 744 drm-engine-video-enhance: 0 ns 745 746Possible `drm-engine-` key names are: `render`, `copy`, `video` and 747`video-enhance`. 748