1=========================== 2 drm/i915 Intel GFX Driver 3=========================== 4 5The drm/i915 driver supports all (with the exception of some very early 6models) integrated GFX chipsets with both Intel display and rendering 7blocks. This excludes a set of SoC platforms with an SGX rendering unit, 8those have basic support through the gma500 drm driver. 9 10Core Driver Infrastructure 11========================== 12 13This section covers core driver infrastructure used by both the display 14and the GEM parts of the driver. 15 16Runtime Power Management 17------------------------ 18 19.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 20 :doc: runtime pm 21 22.. kernel-doc:: drivers/gpu/drm/i915/intel_runtime_pm.c 23 :internal: 24 25.. kernel-doc:: drivers/gpu/drm/i915/intel_uncore.c 26 :internal: 27 28Interrupt Handling 29------------------ 30 31.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 32 :doc: interrupt handling 33 34.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 35 :functions: intel_irq_init intel_irq_init_hw intel_hpd_init 36 37.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 38 :functions: intel_runtime_pm_disable_interrupts 39 40.. kernel-doc:: drivers/gpu/drm/i915/i915_irq.c 41 :functions: intel_runtime_pm_enable_interrupts 42 43Intel GVT-g Guest Support(vGPU) 44------------------------------- 45 46.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 47 :doc: Intel GVT-g guest support 48 49.. kernel-doc:: drivers/gpu/drm/i915/i915_vgpu.c 50 :internal: 51 52Intel GVT-g Host Support(vGPU device model) 53------------------------------------------- 54 55.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 56 :doc: Intel GVT-g host support 57 58.. kernel-doc:: drivers/gpu/drm/i915/intel_gvt.c 59 :internal: 60 61Workarounds 62----------- 63 64.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_workarounds.c 65 :doc: Hardware workarounds 66 67Display Hardware Handling 68========================= 69 70This section covers everything related to the display hardware including 71the mode setting infrastructure, plane, sprite and cursor handling and 72display, output probing and related topics. 73 74Mode Setting Infrastructure 75--------------------------- 76 77The i915 driver is thus far the only DRM driver which doesn't use the 78common DRM helper code to implement mode setting sequences. Thus it has 79its own tailor-made infrastructure for executing a display configuration 80change. 81 82Frontbuffer Tracking 83-------------------- 84 85.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 86 :doc: frontbuffer tracking 87 88.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.h 89 :internal: 90 91.. kernel-doc:: drivers/gpu/drm/i915/display/intel_frontbuffer.c 92 :internal: 93 94Display FIFO Underrun Reporting 95------------------------------- 96 97.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 98 :doc: fifo underrun handling 99 100.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fifo_underrun.c 101 :internal: 102 103Plane Configuration 104------------------- 105 106This section covers plane configuration and composition with the primary 107plane, sprites, cursors and overlays. This includes the infrastructure 108to do atomic vsync'ed updates of all this state and also tightly coupled 109topics like watermark setup and computation, framebuffer compression and 110panel self refresh. 111 112Atomic Plane Helpers 113-------------------- 114 115.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c 116 :doc: atomic plane helpers 117 118.. kernel-doc:: drivers/gpu/drm/i915/display/intel_atomic_plane.c 119 :internal: 120 121Asynchronous Page Flip 122---------------------- 123 124.. kernel-doc:: drivers/gpu/drm/i915/display/intel_display.c 125 :doc: asynchronous flip implementation 126 127Output Probing 128-------------- 129 130This section covers output probing and related infrastructure like the 131hotplug interrupt storm detection and mitigation code. Note that the 132i915 driver still uses most of the common DRM helper code for output 133probing, so those sections fully apply. 134 135Hotplug 136------- 137 138.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 139 :doc: Hotplug 140 141.. kernel-doc:: drivers/gpu/drm/i915/display/intel_hotplug.c 142 :internal: 143 144High Definition Audio 145--------------------- 146 147.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 148 :doc: High Definition Audio over HDMI and Display Port 149 150.. kernel-doc:: drivers/gpu/drm/i915/display/intel_audio.c 151 :internal: 152 153.. kernel-doc:: include/drm/i915_component.h 154 :internal: 155 156Intel HDMI LPE Audio Support 157---------------------------- 158 159.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 160 :doc: LPE Audio integration for HDMI or DP playback 161 162.. kernel-doc:: drivers/gpu/drm/i915/display/intel_lpe_audio.c 163 :internal: 164 165Panel Self Refresh PSR (PSR/SRD) 166-------------------------------- 167 168.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 169 :doc: Panel Self Refresh (PSR/SRD) 170 171.. kernel-doc:: drivers/gpu/drm/i915/display/intel_psr.c 172 :internal: 173 174Frame Buffer Compression (FBC) 175------------------------------ 176 177.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 178 :doc: Frame Buffer Compression (FBC) 179 180.. kernel-doc:: drivers/gpu/drm/i915/display/intel_fbc.c 181 :internal: 182 183Display Refresh Rate Switching (DRRS) 184------------------------------------- 185 186.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 187 :doc: Display Refresh Rate Switching (DRRS) 188 189.. kernel-doc:: drivers/gpu/drm/i915/display/intel_drrs.c 190 :internal: 191 192DPIO 193---- 194 195.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpio_phy.c 196 :doc: DPIO 197 198DMC Firmware Support 199-------------------- 200 201.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c 202 :doc: DMC Firmware Support 203 204.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dmc.c 205 :internal: 206 207Video BIOS Table (VBT) 208---------------------- 209 210.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 211 :doc: Video BIOS Table (VBT) 212 213.. kernel-doc:: drivers/gpu/drm/i915/display/intel_bios.c 214 :internal: 215 216.. kernel-doc:: drivers/gpu/drm/i915/display/intel_vbt_defs.h 217 :internal: 218 219Display clocks 220-------------- 221 222.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 223 :doc: CDCLK / RAWCLK 224 225.. kernel-doc:: drivers/gpu/drm/i915/display/intel_cdclk.c 226 :internal: 227 228Display PLLs 229------------ 230 231.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 232 :doc: Display PLLs 233 234.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.c 235 :internal: 236 237.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dpll_mgr.h 238 :internal: 239 240Display State Buffer 241-------------------- 242 243.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 244 :doc: DSB 245 246.. kernel-doc:: drivers/gpu/drm/i915/display/intel_dsb.c 247 :internal: 248 249Memory Management and Command Submission 250======================================== 251 252This sections covers all things related to the GEM implementation in the 253i915 driver. 254 255Intel GPU Basics 256---------------- 257 258An Intel GPU has multiple engines. There are several engine types. 259 260- RCS engine is for rendering 3D and performing compute, this is named 261 `I915_EXEC_RENDER` in user space. 262- BCS is a blitting (copy) engine, this is named `I915_EXEC_BLT` in user 263 space. 264- VCS is a video encode and decode engine, this is named `I915_EXEC_BSD` 265 in user space 266- VECS is video enhancement engine, this is named `I915_EXEC_VEBOX` in user 267 space. 268- The enumeration `I915_EXEC_DEFAULT` does not refer to specific engine; 269 instead it is to be used by user space to specify a default rendering 270 engine (for 3D) that may or may not be the same as RCS. 271 272The Intel GPU family is a family of integrated GPU's using Unified 273Memory Access. For having the GPU "do work", user space will feed the 274GPU batch buffers via one of the ioctls `DRM_IOCTL_I915_GEM_EXECBUFFER2` 275or `DRM_IOCTL_I915_GEM_EXECBUFFER2_WR`. Most such batchbuffers will 276instruct the GPU to perform work (for example rendering) and that work 277needs memory from which to read and memory to which to write. All memory 278is encapsulated within GEM buffer objects (usually created with the ioctl 279`DRM_IOCTL_I915_GEM_CREATE`). An ioctl providing a batchbuffer for the GPU 280to create will also list all GEM buffer objects that the batchbuffer reads 281and/or writes. For implementation details of memory management see 282`GEM BO Management Implementation Details`_. 283 284The i915 driver allows user space to create a context via the ioctl 285`DRM_IOCTL_I915_GEM_CONTEXT_CREATE` which is identified by a 32-bit 286integer. Such a context should be viewed by user-space as -loosely- 287analogous to the idea of a CPU process of an operating system. The i915 288driver guarantees that commands issued to a fixed context are to be 289executed so that writes of a previously issued command are seen by 290reads of following commands. Actions issued between different contexts 291(even if from the same file descriptor) are NOT given that guarantee 292and the only way to synchronize across contexts (even from the same 293file descriptor) is through the use of fences. At least as far back as 294Gen4, also have that a context carries with it a GPU HW context; 295the HW context is essentially (most of atleast) the state of a GPU. 296In addition to the ordering guarantees, the kernel will restore GPU 297state via HW context when commands are issued to a context, this saves 298user space the need to restore (most of atleast) the GPU state at the 299start of each batchbuffer. The non-deprecated ioctls to submit batchbuffer 300work can pass that ID (in the lower bits of drm_i915_gem_execbuffer2::rsvd1) 301to identify what context to use with the command. 302 303The GPU has its own memory management and address space. The kernel 304driver maintains the memory translation table for the GPU. For older 305GPUs (i.e. those before Gen8), there is a single global such translation 306table, a global Graphics Translation Table (GTT). For newer generation 307GPUs each context has its own translation table, called Per-Process 308Graphics Translation Table (PPGTT). Of important note, is that although 309PPGTT is named per-process it is actually per context. When user space 310submits a batchbuffer, the kernel walks the list of GEM buffer objects 311used by the batchbuffer and guarantees that not only is the memory of 312each such GEM buffer object resident but it is also present in the 313(PP)GTT. If the GEM buffer object is not yet placed in the (PP)GTT, 314then it is given an address. Two consequences of this are: the kernel 315needs to edit the batchbuffer submitted to write the correct value of 316the GPU address when a GEM BO is assigned a GPU address and the kernel 317might evict a different GEM BO from the (PP)GTT to make address room 318for another GEM BO. Consequently, the ioctls submitting a batchbuffer 319for execution also include a list of all locations within buffers that 320refer to GPU-addresses so that the kernel can edit the buffer correctly. 321This process is dubbed relocation. 322 323Locking Guidelines 324------------------ 325 326.. note:: 327 This is a description of how the locking should be after 328 refactoring is done. Does not necessarily reflect what the locking 329 looks like while WIP. 330 331#. All locking rules and interface contracts with cross-driver interfaces 332 (dma-buf, dma_fence) need to be followed. 333 334#. No struct_mutex anywhere in the code 335 336#. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx 337 is to be hoisted at highest level and passed down within i915_gem_ctx 338 in the call chain 339 340#. While holding lru/memory manager (buddy, drm_mm, whatever) locks 341 system memory allocations are not allowed 342 343 * Enforce this by priming lockdep (with fs_reclaim). If we 344 allocate memory while holding these looks we get a rehash 345 of the shrinker vs. struct_mutex saga, and that would be 346 real bad. 347 348#. Do not nest different lru/memory manager locks within each other. 349 Take them in turn to update memory allocations, relying on the object’s 350 dma_resv ww_mutex to serialize against other operations. 351 352#. The suggestion for lru/memory managers locks is that they are small 353 enough to be spinlocks. 354 355#. All features need to come with exhaustive kernel selftests and/or 356 IGT tests when appropriate 357 358#. All LMEM uAPI paths need to be fully restartable (_interruptible() 359 for all locks/waits/sleeps) 360 361 * Error handling validation through signal injection. 362 Still the best strategy we have for validating GEM uAPI 363 corner cases. 364 Must be excessively used in the IGT, and we need to check 365 that we really have full path coverage of all error cases. 366 367 * -EDEADLK handling with ww_mutex 368 369GEM BO Management Implementation Details 370---------------------------------------- 371 372.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 373 :doc: Virtual Memory Address 374 375Buffer Object Eviction 376---------------------- 377 378This section documents the interface functions for evicting buffer 379objects to make space available in the virtual gpu address spaces. Note 380that this is mostly orthogonal to shrinking buffer objects caches, which 381has the goal to make main memory (shared with the gpu through the 382unified memory architecture) available. 383 384.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_evict.c 385 :internal: 386 387Buffer Object Memory Shrinking 388------------------------------ 389 390This section documents the interface function for shrinking memory usage 391of buffer object caches. Shrinking is used to make main memory 392available. Note that this is mostly orthogonal to evicting buffer 393objects, which has the goal to make space in gpu virtual address spaces. 394 395.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_shrinker.c 396 :internal: 397 398Batchbuffer Parsing 399------------------- 400 401.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 402 :doc: batch buffer command parser 403 404.. kernel-doc:: drivers/gpu/drm/i915/i915_cmd_parser.c 405 :internal: 406 407User Batchbuffer Execution 408-------------------------- 409 410.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_context_types.h 411 412.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c 413 :doc: User command execution 414 415Scheduling 416---------- 417.. kernel-doc:: drivers/gpu/drm/i915/i915_scheduler_types.h 418 :functions: i915_sched_engine 419 420Logical Rings, Logical Ring Contexts and Execlists 421-------------------------------------------------- 422 423.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_execlists_submission.c 424 :doc: Logical Rings, Logical Ring Contexts and Execlists 425 426Global GTT views 427---------------- 428 429.. kernel-doc:: drivers/gpu/drm/i915/i915_vma_types.h 430 :doc: Global GTT views 431 432.. kernel-doc:: drivers/gpu/drm/i915/i915_gem_gtt.c 433 :internal: 434 435GTT Fences and Swizzling 436------------------------ 437 438.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 439 :internal: 440 441Global GTT Fence Handling 442~~~~~~~~~~~~~~~~~~~~~~~~~ 443 444.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 445 :doc: fence register handling 446 447Hardware Tiling and Swizzling Details 448~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 449 450.. kernel-doc:: drivers/gpu/drm/i915/gt/intel_ggtt_fencing.c 451 :doc: tiling swizzling details 452 453Object Tiling IOCTLs 454-------------------- 455 456.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 457 :internal: 458 459.. kernel-doc:: drivers/gpu/drm/i915/gem/i915_gem_tiling.c 460 :doc: buffer object tiling 461 462Protected Objects 463----------------- 464 465.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp.c 466 :doc: PXP 467 468.. kernel-doc:: drivers/gpu/drm/i915/pxp/intel_pxp_types.h 469 470Microcontrollers 471================ 472 473Starting from gen9, three microcontrollers are available on the HW: the 474graphics microcontroller (GuC), the HEVC/H.265 microcontroller (HuC) and the 475display microcontroller (DMC). The driver is responsible for loading the 476firmwares on the microcontrollers; the GuC and HuC firmwares are transferred 477to WOPCM using the DMA engine, while the DMC firmware is written through MMIO. 478 479WOPCM 480----- 481 482WOPCM Layout 483~~~~~~~~~~~~ 484 485.. kernel-doc:: drivers/gpu/drm/i915/intel_wopcm.c 486 :doc: WOPCM Layout 487 488GuC 489--- 490 491.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 492 :doc: GuC 493 494.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.h 495 496GuC Firmware Layout 497~~~~~~~~~~~~~~~~~~~ 498 499.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h 500 :doc: Firmware Layout 501 502GuC Memory Management 503~~~~~~~~~~~~~~~~~~~~~ 504 505.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 506 :doc: GuC Memory Management 507.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc.c 508 :functions: intel_guc_allocate_vma 509 510 511GuC-specific firmware loader 512~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 513 514.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_fw.c 515 :internal: 516 517GuC-based command submission 518~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 519 520.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c 521 :doc: GuC-based command submission 522 523GuC ABI 524~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 525 526.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h 527.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h 528.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h 529.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h 530.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h 531 532HuC 533--- 534.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 535 :doc: HuC 536.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 537 :functions: intel_huc_auth 538 539HuC Memory Management 540~~~~~~~~~~~~~~~~~~~~~ 541 542.. kernel-doc:: drivers/gpu/drm/i915/gt/uc/intel_huc.c 543 :doc: HuC Memory Management 544 545HuC Firmware Layout 546~~~~~~~~~~~~~~~~~~~ 547The HuC FW layout is the same as the GuC one, see `GuC Firmware Layout`_ 548 549DMC 550--- 551See `DMC Firmware Support`_ 552 553Tracing 554======= 555 556This sections covers all things related to the tracepoints implemented 557in the i915 driver. 558 559i915_ppgtt_create and i915_ppgtt_release 560---------------------------------------- 561 562.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 563 :doc: i915_ppgtt_create and i915_ppgtt_release tracepoints 564 565i915_context_create and i915_context_free 566----------------------------------------- 567 568.. kernel-doc:: drivers/gpu/drm/i915/i915_trace.h 569 :doc: i915_context_create and i915_context_free tracepoints 570 571Perf 572==== 573 574Overview 575-------- 576.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 577 :doc: i915 Perf Overview 578 579Comparison with Core Perf 580------------------------- 581.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 582 :doc: i915 Perf History and Comparison with Core Perf 583 584i915 Driver Entry Points 585------------------------ 586 587This section covers the entrypoints exported outside of i915_perf.c to 588integrate with drm/i915 and to handle the `DRM_I915_PERF_OPEN` ioctl. 589 590.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 591 :functions: i915_perf_init 592.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 593 :functions: i915_perf_fini 594.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 595 :functions: i915_perf_register 596.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 597 :functions: i915_perf_unregister 598.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 599 :functions: i915_perf_open_ioctl 600.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 601 :functions: i915_perf_release 602.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 603 :functions: i915_perf_add_config_ioctl 604.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 605 :functions: i915_perf_remove_config_ioctl 606 607i915 Perf Stream 608---------------- 609 610This section covers the stream-semantics-agnostic structures and functions 611for representing an i915 perf stream FD and associated file operations. 612 613.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 614 :functions: i915_perf_stream 615.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 616 :functions: i915_perf_stream_ops 617 618.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 619 :functions: read_properties_unlocked 620.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 621 :functions: i915_perf_open_ioctl_locked 622.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 623 :functions: i915_perf_destroy_locked 624.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 625 :functions: i915_perf_read 626.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 627 :functions: i915_perf_ioctl 628.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 629 :functions: i915_perf_enable_locked 630.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 631 :functions: i915_perf_disable_locked 632.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 633 :functions: i915_perf_poll 634.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 635 :functions: i915_perf_poll_locked 636 637i915 Perf Observation Architecture Stream 638----------------------------------------- 639 640.. kernel-doc:: drivers/gpu/drm/i915/i915_perf_types.h 641 :functions: i915_oa_ops 642 643.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 644 :functions: i915_oa_stream_init 645.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 646 :functions: i915_oa_read 647.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 648 :functions: i915_oa_stream_enable 649.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 650 :functions: i915_oa_stream_disable 651.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 652 :functions: i915_oa_wait_unlocked 653.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 654 :functions: i915_oa_poll_wait 655 656Other i915 Perf Internals 657------------------------- 658 659This section simply includes all other currently documented i915 perf internals, 660in no particular order, but may include some more minor utilities or platform 661specific details than found in the more high-level sections. 662 663.. kernel-doc:: drivers/gpu/drm/i915/i915_perf.c 664 :internal: 665 :no-identifiers: 666 i915_perf_init 667 i915_perf_fini 668 i915_perf_register 669 i915_perf_unregister 670 i915_perf_open_ioctl 671 i915_perf_release 672 i915_perf_add_config_ioctl 673 i915_perf_remove_config_ioctl 674 read_properties_unlocked 675 i915_perf_open_ioctl_locked 676 i915_perf_destroy_locked 677 i915_perf_read i915_perf_ioctl 678 i915_perf_enable_locked 679 i915_perf_disable_locked 680 i915_perf_poll i915_perf_poll_locked 681 i915_oa_stream_init i915_oa_read 682 i915_oa_stream_enable 683 i915_oa_stream_disable 684 i915_oa_wait_unlocked 685 i915_oa_poll_wait 686 687Style 688===== 689 690The drm/i915 driver codebase has some style rules in addition to (and, in some 691cases, deviating from) the kernel coding style. 692 693Register macro definition style 694------------------------------- 695 696The style guide for ``i915_reg.h``. 697 698.. kernel-doc:: drivers/gpu/drm/i915/i915_reg.h 699 :doc: The i915 register macro definition style guide 700 701.. _i915-usage-stats: 702 703i915 DRM client usage stats implementation 704========================================== 705 706The drm/i915 driver implements the DRM client usage stats specification as 707documented in :ref:`drm-client-usage-stats`. 708 709Example of the output showing the implemented key value pairs and entirety of 710the currently possible format options: 711 712:: 713 714 pos: 0 715 flags: 0100002 716 mnt_id: 21 717 drm-driver: i915 718 drm-pdev: 0000:00:02.0 719 drm-client-id: 7 720 drm-engine-render: 9288864723 ns 721 drm-engine-copy: 2035071108 ns 722 drm-engine-video: 0 ns 723 drm-engine-capacity-video: 2 724 drm-engine-video-enhance: 0 ns 725 726Possible `drm-engine-` key names are: `render`, `copy`, `video` and 727`video-enhance`. 728