1*74f0ff36SRodrigo Siqueira.. _amdgpu-mes: 2*74f0ff36SRodrigo Siqueira 3*74f0ff36SRodrigo Siqueira============================= 4*74f0ff36SRodrigo Siqueira MicroEngine Scheduler (MES) 5*74f0ff36SRodrigo Siqueira============================= 6*74f0ff36SRodrigo Siqueira 7*74f0ff36SRodrigo Siqueira.. note:: 8*74f0ff36SRodrigo Siqueira Queue and ring buffer are used as a synonymous. 9*74f0ff36SRodrigo Siqueira 10*74f0ff36SRodrigo Siqueira.. note:: 11*74f0ff36SRodrigo Siqueira This section assumes that you are familiar with the concept of Pipes, Queues, and GC. 12*74f0ff36SRodrigo Siqueira If not, check :ref:`GFX, Compute, and SDMA Overall Behavior<pipes-and-queues-description>` 13*74f0ff36SRodrigo Siqueira and :ref:`drm/amdgpu - Graphics and Compute (GC) <amdgpu-gc>`. 14*74f0ff36SRodrigo Siqueira 15*74f0ff36SRodrigo SiqueiraEvery GFX has a pipe component with one or more hardware queues. Pipes can 16*74f0ff36SRodrigo Siqueiraswitch between queues depending on certain conditions, and one of the 17*74f0ff36SRodrigo Siqueiracomponents that can request a queue switch to a pipe is the MicroEngine 18*74f0ff36SRodrigo SiqueiraScheduler (MES). Whenever the driver is initialized, it creates one MQD per 19*74f0ff36SRodrigo Siqueirahardware queue, and then the MQDs are handed to the MES firmware for mapping 20*74f0ff36SRodrigo Siqueirato: 21*74f0ff36SRodrigo Siqueira 22*74f0ff36SRodrigo Siqueira1. Kernel Queues (legacy): This queue is statically mapped to HQDs and never 23*74f0ff36SRodrigo Siqueira preempted. Even though this is a legacy feature, it is the current default, and 24*74f0ff36SRodrigo Siqueira most existing hardware supports it. When an application submits work to the 25*74f0ff36SRodrigo Siqueira kernel driver, it submits all of the application command buffers to the kernel 26*74f0ff36SRodrigo Siqueira queues. The CS IOCTL takes the command buffer from the applications and 27*74f0ff36SRodrigo Siqueira schedules them on the kernel queue. 28*74f0ff36SRodrigo Siqueira 29*74f0ff36SRodrigo Siqueira2. User Queues: These queues are dynamically mapped to the HQDs. Regarding the 30*74f0ff36SRodrigo Siqueira utilization of User Queues, the userspace application will create its user 31*74f0ff36SRodrigo Siqueira queues and submit work directly to its user queues with no need to IOCTL for 32*74f0ff36SRodrigo Siqueira each submission and no need to share a single kernel queue. 33*74f0ff36SRodrigo Siqueira 34*74f0ff36SRodrigo SiqueiraIn terms of User Queues, MES can dynamically map them to the HQD. If there are 35*74f0ff36SRodrigo Siqueiramore MQDs than HQDs, the MES firmware will preempt other user queues to make 36*74f0ff36SRodrigo Siqueirasure each queues get a time slice; in other words, MES is a microcontroller 37*74f0ff36SRodrigo Siqueirathat handles the mapping and unmapping of MQDs into HQDs, as well as the 38*74f0ff36SRodrigo Siqueirapriorities and oversubscription of MQDs. 39