1.. _amdgpu-gc: 2 3======================================== 4 drm/amdgpu - Graphics and Compute (GC) 5======================================== 6 7The relationship between the CPU and GPU can be described as the 8producer-consumer problem, where the CPU fills out a buffer with operations 9(producer) to be executed by the GPU (consumer). The requested operations in 10the buffer are called **Command Packets**, which can be summarized as a 11compressed way of transmitting command information to the graphics controller. 12 13The component that acts as the front end between the CPU and the GPU is called 14**Command Processor (CP)**. This component is responsible for providing greater 15flexibility to the **Graphics and Compute (GC)** since CP makes it possible to 16program various aspects of the GPU pipeline. CP also coordinates the 17communication between the CPU and GPU via a mechanism named **Ring Buffers**, 18where the CPU appends information to the buffer while the GPU removes 19operations. CP is also responsible for handling **Indirect Buffers (IB)**. 20 21For reference, internally the CP consists of several sub-blocks (CPC - CP 22compute, CPG - CP graphics, and CPF - CP fetcher). Some of these acronyms 23appear in register names, but this is more of an implementation detail and not 24something that directly impacts driver programming or debugging. 25 26Graphics (GFX) and Compute Microcontrollers 27------------------------------------------- 28 29GC is a large block, and as a result, it has multiple firmware associated with 30it. Some of them are: 31 32CP (Command Processor) 33 The name for the hardware block that encompasses the front end of the 34 GFX/Compute pipeline. Consists mainly of a bunch of microcontrollers 35 (PFP, ME, CE, MEC). The firmware that runs on these microcontrollers 36 provides the driver interface to interact with the GFX/Compute engine. 37 38 MEC (MicroEngine Compute) 39 This is the microcontroller that controls the compute queues on the 40 GFX/compute engine. 41 42 MES (MicroEngine Scheduler) 43 This is the engine for managing queues. For more details check 44 :ref:`MicroEngine Scheduler (MES) <amdgpu-mes>`. 45 46RLC (RunList Controller) 47 This is another microcontroller in the GFX/Compute engine. It handles 48 power management related functionality within the GFX/Compute engine. 49 The name is a vestige of old hardware where it was originally added 50 and doesn't really have much relation to what the engine does now. 51 52.. toctree:: 53 54 mes.rst 55