1============================ 2 Core Driver Infrastructure 3============================ 4 5GPU Hardware Structure 6====================== 7 8Each ASIC is a collection of hardware blocks. We refer to them as 9"IPs" (Intellectual Property blocks). Each IP encapsulates certain 10functionality. IPs are versioned and can also be mixed and matched. 11E.g., you might have two different ASICs that both have System DMA (SDMA) 5.x IPs. 12The driver is arranged by IPs. There are driver components to handle 13the initialization and operation of each IP. There are also a bunch 14of smaller IPs that don't really need much if any driver interaction. 15Those end up getting lumped into the common stuff in the soc files. 16The soc files (e.g., vi.c, soc15.c nv.c) contain code for aspects of 17the SoC itself rather than specific IPs. E.g., things like GPU resets 18and register access functions are SoC dependent. 19 20An APU contains more than just CPU and GPU, it also contains all of 21the platform stuff (audio, usb, gpio, etc.). Also, a lot of 22components are shared between the CPU, platform, and the GPU (e.g., 23SMU, PSP, etc.). Specific components (CPU, GPU, etc.) usually have 24their interface to interact with those common components. For things 25like S0i3 there is a ton of coordination required across all the 26components, but that is probably a bit beyond the scope of this 27section. 28 29With respect to the GPU, we have the following major IPs: 30 31GMC (Graphics Memory Controller) 32 This was a dedicated IP on older pre-vega chips, but has since 33 become somewhat decentralized on vega and newer chips. They now 34 have dedicated memory hubs for specific IPs or groups of IPs. We 35 still treat it as a single component in the driver however since 36 the programming model is still pretty similar. This is how the 37 different IPs on the GPU get the memory (VRAM or system memory). 38 It also provides the support for per process GPU virtual address 39 spaces. 40 41IH (Interrupt Handler) 42 This is the interrupt controller on the GPU. All of the IPs feed 43 their interrupts into this IP and it aggregates them into a set of 44 ring buffers that the driver can parse to handle interrupts from 45 different IPs. 46 47PSP (Platform Security Processor) 48 This handles security policy for the SoC and executes trusted 49 applications, and validates and loads firmwares for other blocks. 50 51SMU (System Management Unit) 52 This is the power management microcontroller. It manages the entire 53 SoC. The driver interacts with it to control power management 54 features like clocks, voltages, power rails, etc. 55 56DCN (Display Controller Next) 57 This is the display controller. It handles the display hardware. 58 It is described in more details in :ref:`Display Core <amdgpu-display-core>`. 59 60SDMA (System DMA) 61 This is a multi-purpose DMA engine. The kernel driver uses it for 62 various things including paging and GPU page table updates. It's also 63 exposed to userspace for use by user mode drivers (OpenGL, Vulkan, 64 etc.) 65 66GC (Graphics and Compute) 67 This is the graphics and compute engine, i.e., the block that 68 encompasses the 3D pipeline and and shader blocks. This is by far the 69 largest block on the GPU. The 3D pipeline has tons of sub-blocks. In 70 addition to that, it also contains the CP microcontrollers (ME, PFP, CE, 71 MEC) and the RLC microcontroller. It's exposed to userspace for user mode 72 drivers (OpenGL, Vulkan, OpenCL, etc.). More details in :ref:`Graphics (GFX) 73 and Compute <amdgpu-gc>`. 74 75VCN (Video Core Next) 76 This is the multi-media engine. It handles video and image encode and 77 decode. It's exposed to userspace for user mode drivers (VA-API, 78 OpenMAX, etc.) 79 80GFX, Compute, and SDMA Overall Behavior 81======================================= 82 83.. note:: For simplicity, whenever the term block is used in this section, it 84 means GFX, Compute, and SDMA. 85 86GFX, Compute and SDMA share a similar form of operation that can be abstracted 87to facilitate understanding of the behavior of these blocks. See the figure 88below illustrating the common components of these blocks: 89 90.. kernel-figure:: pipe_and_queue_abstraction.svg 91 92In the central part of this figure, you can see two hardware elements, one called 93**Pipes** and another called **Queues**; it is important to highlight that Queues 94must be associated with a Pipe and vice-versa. Every specific hardware IP may have 95a different number of Pipes and, in turn, a different number of Queues; for 96example, GFX 11 has two Pipes and two Queues per Pipe for the GFX front end. 97 98Pipe is the hardware that processes the instructions available in the Queues; 99in other words, it is a thread executing the operations inserted in the Queue. 100One crucial characteristic of Pipes is that they can only execute one Queue at 101a time; no matter if the hardware has multiple Queues in the Pipe, it only runs 102one Queue per Pipe. 103 104Pipes have the mechanics of swapping between queues at the hardware level. 105Nonetheless, they only make use of Queues that are considered mapped. Pipes can 106switch between queues based on any of the following inputs: 107 1081. Command Stream; 1092. Packet by Packet; 1103. Other hardware requests the change (e.g., MES). 111 112Queues within Pipes are defined by the Hardware Queue Descriptors (HQD). 113Associated with the HQD concept, we have the Memory Queue Descriptor (MQD), 114which is responsible for storing information about the state of each of the 115available Queues in the memory. The state of a Queue contains information such 116as the GPU virtual address of the queue itself, save areas, doorbell, etc. The 117MQD also stores the HQD registers, which are vital for activating or 118deactivating a given Queue. The scheduling firmware (e.g., MES) is responsible 119for loading HQDs from MQDs and vice versa. 120 121The Queue-switching process can also happen with the firmware requesting the 122preemption or unmapping of a Queue. The firmware waits for the HQD_ACTIVE bit 123to change to low before saving the state into the MQD. To make a different 124Queue become active, the firmware copies the MQD state into the HQD registers 125and loads any additional state. Finally, it sets the HQD_ACTIVE bit to high to 126indicate that the queue is active. The Pipe will then execute work from active 127Queues. 128 129Driver Structure 130================ 131 132In general, the driver has a list of all of the IPs on a particular 133SoC and for things like init/fini/suspend/resume, more or less just 134walks the list and handles each IP. 135 136Some useful constructs: 137 138KIQ (Kernel Interface Queue) 139 This is a control queue used by the kernel driver to manage other gfx 140 and compute queues on the GFX/compute engine. You can use it to 141 map/unmap additional queues, etc. 142 143IB (Indirect Buffer) 144 A command buffer for a particular engine. Rather than writing 145 commands directly to the queue, you can write the commands into a 146 piece of memory and then put a pointer to the memory into the queue. 147 The hardware will then follow the pointer and execute the commands in 148 the memory, then returning to the rest of the commands in the ring. 149 150.. _amdgpu_memory_domains: 151 152Memory Domains 153============== 154 155.. kernel-doc:: include/uapi/drm/amdgpu_drm.h 156 :doc: memory domains 157 158Buffer Objects 159============== 160 161.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 162 :doc: amdgpu_object 163 164.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_object.c 165 :internal: 166 167PRIME Buffer Sharing 168==================== 169 170.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c 171 :doc: PRIME Buffer Sharing 172 173.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.c 174 :internal: 175 176MMU Notifier 177============ 178 179.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c 180 :doc: MMU Notifier 181 182.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.c 183 :internal: 184 185AMDGPU Virtual Memory 186===================== 187 188.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 189 :doc: GPUVM 190 191.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c 192 :internal: 193 194Interrupt Handling 195================== 196 197.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 198 :doc: Interrupt Handling 199 200.. kernel-doc:: drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c 201 :internal: 202 203IP Blocks 204========= 205 206.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h 207 :doc: IP Blocks 208 209.. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h 210 :identifiers: amd_ip_block_type amd_ip_funcs DC_DEBUG_MASK 211
