1=============== 2AMDGPU Glossary 3=============== 4 5Here you can find some generic acronyms used in the amdgpu driver. Notice that 6we have a dedicated glossary for Display Core at 7'Documentation/gpu/amdgpu/display/dc-glossary.rst'. 8 9.. glossary:: 10 11 active_cu_number 12 The number of CUs that are active on the system. The number of active 13 CUs may be less than SE * SH * CU depending on the board configuration. 14 15 BACO 16 Bus Alive, Chip Off 17 18 BOCO 19 Bus Off, Chip Off 20 21 CE 22 Constant Engine 23 24 CIK 25 Sea Islands 26 27 CB 28 Color Buffer 29 30 CP 31 Command Processor 32 33 CPC 34 Command Processor Compute 35 36 CPF 37 Command Processor Fetch 38 39 CPG 40 Command Processor Graphics 41 42 CPLIB 43 Content Protection Library 44 45 CS 46 Command Submission 47 48 CSB 49 Clear State Indirect Buffer 50 51 CU 52 Compute Unit 53 54 DB 55 Depth Buffer 56 57 DFS 58 Digital Frequency Synthesizer 59 60 ECP 61 Enhanced Content Protection 62 63 EOP 64 End Of Pipe/Pipeline 65 66 FLR 67 Function Level Reset 68 69 GART 70 Graphics Address Remapping Table. This is the name we use for the GPUVM 71 page table used by the GPU kernel driver. It remaps system resources 72 (memory or MMIO space) into the GPU's address space so the GPU can access 73 them. The name GART harkens back to the days of AGP when the platform 74 provided an MMU that the GPU could use to get a contiguous view of 75 scattered pages for DMA. The MMU has since moved on to the GPU, but the 76 name stuck. 77 78 GC 79 Graphics and Compute 80 81 GDS 82 Global Data Share 83 84 GE 85 Geometry Engine 86 87 GMC 88 Graphic Memory Controller 89 90 GPR 91 General Purpose Register 92 93 GPUVM 94 GPU Virtual Memory. This is the GPU's MMU. The GPU supports multiple 95 virtual address spaces that can be in flight at any given time. These 96 allow the GPU to remap VRAM and system resources into GPU virtual address 97 spaces for use by the GPU kernel driver and applications using the GPU. 98 These provide memory protection for different applications using the GPU. 99 100 GTT 101 Graphics Translation Tables. This is a memory pool managed through TTM 102 which provides access to system resources (memory or MMIO space) for 103 use by the GPU. These addresses can be mapped into the "GART" GPUVM page 104 table for use by the kernel driver or into per process GPUVM page tables 105 for application usage. 106 107 GWS 108 Global Wave Sync 109 110 IH 111 Interrupt Handler 112 113 IV 114 Interrupt Vector 115 116 HQD 117 Hardware Queue Descriptor 118 119 IB 120 Indirect Buffer 121 122 IMU 123 Integrated Management Unit (Power Management support) 124 125 IP 126 Intellectual Property blocks 127 128 KCQ 129 Kernel Compute Queue 130 131 KFD 132 Kernel Fusion Driver 133 134 KGQ 135 Kernel Graphics Queue 136 137 KIQ 138 Kernel Interface Queue 139 140 MC 141 Memory Controller 142 143 MCBP 144 Mid Command Buffer Preemption 145 146 ME 147 MicroEngine (Graphics) 148 149 MEC 150 MicroEngine Compute 151 152 MES 153 MicroEngine Scheduler 154 155 MMHUB 156 Multi-Media HUB 157 158 MQD 159 Memory Queue Descriptor 160 161 PA 162 Primitive Assembler / Physical Address 163 164 PDE 165 Page Directory Entry 166 167 PFP 168 Pre-Fetch Parser (Graphics) 169 170 PPLib 171 PowerPlay Library - PowerPlay is the power management component. 172 173 PRT 174 Partially Resident Texture (also known as sparse residency) 175 176 PSP 177 Platform Security Processor 178 179 PTE 180 Page Table Entry 181 182 RB 183 Render Backends. Some people called it ROPs. 184 185 RLC 186 RunList Controller. This name is a remnant of past ages and doesn't have 187 much meaning today. It's a group of general-purpose helper engines for 188 the GFX block. It's involved in GFX power management and SR-IOV, among 189 other things. 190 191 SC 192 Scan Converter 193 194 SDMA 195 System DMA 196 197 SE 198 Shader Engine 199 200 SGPR 201 Scalar General-Purpose Registers 202 203 SH 204 SHader array 205 206 SI 207 Southern Islands 208 209 SMU/SMC 210 System Management Unit / System Management Controller 211 212 SPI (AMDGPU) 213 Shader Processor Input 214 215 SRLC 216 Save/Restore List Control 217 218 SRLG 219 Save/Restore List GPM_MEM 220 221 SRLS 222 Save/Restore List SRM_MEM 223 224 SS 225 Spread Spectrum 226 227 SX 228 Shader Export 229 230 TA 231 Trusted Application 232 233 TC 234 Texture Cache 235 236 TCP (AMDGPU) 237 Texture Cache per Pipe. Even though the name "Texture" is part of this 238 acronym, the TCP represents the path to memory shaders; i.e., it is not 239 related to texture. The name is a leftover from older designs where shader 240 stages had different cache designs; it refers to the L1 cache in older 241 architectures. 242 243 TMR 244 Trusted Memory Region 245 246 TMZ 247 Trusted Memory Zone 248 249 TOC 250 Table of Contents 251 252 UMC 253 Unified Memory Controller 254 255 UMSCH 256 User Mode Scheduler 257 258 UTC (AMDGPU) 259 Unified Translation Cache. UTC is equivalent to TLB. You might see a 260 variation of this acronym with L at the end, i.e., UTCL followed by a 261 number; L means the cache level (e.g., UTCL1 and UTCL2). 262 263 UVD 264 Unified Video Decoder 265 266 VCE 267 Video Compression Engine 268 269 VCN 270 Video Codec Next 271 272 VGPR 273 Vector General-Purpose Registers 274 275 VMID 276 Virtual Memory ID 277 278 VPE 279 Video Processing Engine 280 281 XCC 282 Accelerator Core Complex 283 284 XCP 285 Accelerator Core Partition 286