xref: /linux/Documentation/gpu/amdgpu/amdgpu-glossary.rst (revision c0d4cc9007971f7412f7ee4cbbe98b06b7da813f)
1===============
2AMDGPU Glossary
3===============
4
5Here you can find some generic acronyms used in the amdgpu driver. Notice that
6we have a dedicated glossary for Display Core at
7'Documentation/gpu/amdgpu/display/dc-glossary.rst'.
8
9.. glossary::
10
11    active_cu_number
12      The number of CUs that are active on the system.  The number of active
13      CUs may be less than SE * SH * CU depending on the board configuration.
14
15    BACO
16      Bus Alive, Chip Off
17
18    BOCO
19      Bus Off, Chip Off
20
21    CE
22      Constant Engine
23
24    CIK
25      Sea Islands
26
27    CB
28      Color Buffer
29
30    CP
31      Command Processor
32
33    CPLIB
34      Content Protection Library
35
36    CS
37      Command Submission
38
39    CSB
40      Clear State Indirect Buffer
41
42    CU
43      Compute Unit
44
45    DB
46      Depth Buffer
47
48    DFS
49      Digital Frequency Synthesizer
50
51    ECP
52      Enhanced Content Protection
53
54    EOP
55      End Of Pipe/Pipeline
56
57    FLR
58      Function Level Reset
59
60    GART
61      Graphics Address Remapping Table.  This is the name we use for the GPUVM
62      page table used by the GPU kernel driver.  It remaps system resources
63      (memory or MMIO space) into the GPU's address space so the GPU can access
64      them.  The name GART harkens back to the days of AGP when the platform
65      provided an MMU that the GPU could use to get a contiguous view of
66      scattered pages for DMA.  The MMU has since moved on to the GPU, but the
67      name stuck.
68
69    GC
70      Graphics and Compute
71
72    GDS
73      Global Data Share
74
75    GE
76      Geometry Engine
77
78    GMC
79      Graphic Memory Controller
80
81    GPUVM
82      GPU Virtual Memory.  This is the GPU's MMU.  The GPU supports multiple
83      virtual address spaces that can be in flight at any given time.  These
84      allow the GPU to remap VRAM and system resources into GPU virtual address
85      spaces for use by the GPU kernel driver and applications using the GPU.
86      These provide memory protection for different applications using the GPU.
87
88    GTT
89      Graphics Translation Tables.  This is a memory pool managed through TTM
90      which provides access to system resources (memory or MMIO space) for
91      use by the GPU. These addresses can be mapped into the "GART" GPUVM page
92      table for use by the kernel driver or into per process GPUVM page tables
93      for application usage.
94
95    IH
96      Interrupt Handler
97
98    HQD
99      Hardware Queue Descriptor
100
101    IB
102      Indirect Buffer
103
104    IMU
105      Integrated Management Unit (Power Management support)
106
107    IP
108        Intellectual Property blocks
109
110    KCQ
111      Kernel Compute Queue
112
113    KFD
114      Kernel Fusion Driver
115
116    KGQ
117      Kernel Graphics Queue
118
119    KIQ
120      Kernel Interface Queue
121
122    MC
123      Memory Controller
124
125    MCBP
126      Mid Command Buffer Preemption
127
128    ME
129      MicroEngine (Graphics)
130
131    MEC
132      MicroEngine Compute
133
134    MES
135      MicroEngine Scheduler
136
137    MMHUB
138      Multi-Media HUB
139
140    MQD
141      Memory Queue Descriptor
142
143    PA
144      Primitive Assembler / Physical Address
145
146    PDE
147      Page Directory Entry
148
149    PFP
150      Pre-Fetch Parser (Graphics)
151
152    PPLib
153      PowerPlay Library - PowerPlay is the power management component.
154
155    PRT
156      Partially Resident Texture (also known as sparse residency)
157
158    PSP
159        Platform Security Processor
160
161    PTE
162      Page Table Entry
163
164    RB
165      Render Backends. Some people called it ROPs.
166
167    RLC
168      RunList Controller. This name is a remnant of past ages and doesn't have
169      much meaning today. It's a group of general-purpose helper engines for
170      the GFX block. It's involved in GFX power management and SR-IOV, among
171      other things.
172
173    SC
174      Scan Converter
175
176    SDMA
177      System DMA
178
179    SE
180      Shader Engine
181
182    SGPR
183      Scalar General-Purpose Registers
184
185    SH
186      SHader array
187
188    SI
189      Southern Islands
190
191    SMU/SMC
192      System Management Unit / System Management Controller
193
194    SPI (AMDGPU)
195      Shader Processor Input
196
197    SRLC
198      Save/Restore List Control
199
200    SRLG
201      Save/Restore List GPM_MEM
202
203    SRLS
204      Save/Restore List SRM_MEM
205
206    SS
207      Spread Spectrum
208
209    SX
210      Shader Export
211
212    TA
213      Trusted Application
214
215    TC
216      Texture Cache
217
218    TOC
219      Table of Contents
220
221    UMSCH
222      User Mode Scheduler
223
224    UVD
225      Unified Video Decoder
226
227    VCE
228      Video Compression Engine
229
230    VCN
231      Video Codec Next
232
233    VGPR
234      Vector General-Purpose Registers
235
236    VMID
237      Virtual Memory ID
238
239    VPE
240      Video Processing Engine
241
242    XCC
243      Accelerator Core Complex
244
245    XCP
246      Accelerator Core Partition
247