xref: /linux/Documentation/firmware-guide/acpi/chromeos-acpi-device.rst (revision 0a4cad9c11ad46662ede48d94f08ecb7cd9f6916)
1*0a4cad9cSEnric Balletbo i Serra.. SPDX-License-Identifier: GPL-2.0
2*0a4cad9cSEnric Balletbo i Serra
3*0a4cad9cSEnric Balletbo i Serra=====================
4*0a4cad9cSEnric Balletbo i SerraChrome OS ACPI Device
5*0a4cad9cSEnric Balletbo i Serra=====================
6*0a4cad9cSEnric Balletbo i Serra
7*0a4cad9cSEnric Balletbo i SerraHardware functionality specific to Chrome OS is exposed through a Chrome OS ACPI device.
8*0a4cad9cSEnric Balletbo i SerraThe plug and play ID of a Chrome OS ACPI device is GGL0001. GGL is a valid PNP ID of Google.
9*0a4cad9cSEnric Balletbo i SerraPNP ID can be used with the ACPI devices according to the guidelines. The following ACPI
10*0a4cad9cSEnric Balletbo i Serraobjects are supported:
11*0a4cad9cSEnric Balletbo i Serra
12*0a4cad9cSEnric Balletbo i Serra.. flat-table:: Supported ACPI Objects
13*0a4cad9cSEnric Balletbo i Serra   :widths: 1 2
14*0a4cad9cSEnric Balletbo i Serra   :header-rows: 1
15*0a4cad9cSEnric Balletbo i Serra
16*0a4cad9cSEnric Balletbo i Serra   * - Object
17*0a4cad9cSEnric Balletbo i Serra     - Description
18*0a4cad9cSEnric Balletbo i Serra
19*0a4cad9cSEnric Balletbo i Serra   * - CHSW
20*0a4cad9cSEnric Balletbo i Serra     - Chrome OS switch positions
21*0a4cad9cSEnric Balletbo i Serra
22*0a4cad9cSEnric Balletbo i Serra   * - HWID
23*0a4cad9cSEnric Balletbo i Serra     - Chrome OS hardware ID
24*0a4cad9cSEnric Balletbo i Serra
25*0a4cad9cSEnric Balletbo i Serra   * - FWID
26*0a4cad9cSEnric Balletbo i Serra     - Chrome OS firmware version
27*0a4cad9cSEnric Balletbo i Serra
28*0a4cad9cSEnric Balletbo i Serra   * - FRID
29*0a4cad9cSEnric Balletbo i Serra     - Chrome OS read-only firmware version
30*0a4cad9cSEnric Balletbo i Serra
31*0a4cad9cSEnric Balletbo i Serra   * - BINF
32*0a4cad9cSEnric Balletbo i Serra     - Chrome OS boot information
33*0a4cad9cSEnric Balletbo i Serra
34*0a4cad9cSEnric Balletbo i Serra   * - GPIO
35*0a4cad9cSEnric Balletbo i Serra     - Chrome OS GPIO assignments
36*0a4cad9cSEnric Balletbo i Serra
37*0a4cad9cSEnric Balletbo i Serra   * - VBNV
38*0a4cad9cSEnric Balletbo i Serra     - Chrome OS NVRAM locations
39*0a4cad9cSEnric Balletbo i Serra
40*0a4cad9cSEnric Balletbo i Serra   * - VDTA
41*0a4cad9cSEnric Balletbo i Serra     - Chrome OS verified boot data
42*0a4cad9cSEnric Balletbo i Serra
43*0a4cad9cSEnric Balletbo i Serra   * - FMAP
44*0a4cad9cSEnric Balletbo i Serra     - Chrome OS flashmap base address
45*0a4cad9cSEnric Balletbo i Serra
46*0a4cad9cSEnric Balletbo i Serra   * - MLST
47*0a4cad9cSEnric Balletbo i Serra     - Chrome OS method list
48*0a4cad9cSEnric Balletbo i Serra
49*0a4cad9cSEnric Balletbo i SerraCHSW (Chrome OS switch positions)
50*0a4cad9cSEnric Balletbo i Serra=================================
51*0a4cad9cSEnric Balletbo i SerraThis control method returns the switch positions for Chrome OS specific hardware switches.
52*0a4cad9cSEnric Balletbo i Serra
53*0a4cad9cSEnric Balletbo i SerraArguments:
54*0a4cad9cSEnric Balletbo i Serra----------
55*0a4cad9cSEnric Balletbo i SerraNone
56*0a4cad9cSEnric Balletbo i Serra
57*0a4cad9cSEnric Balletbo i SerraResult code:
58*0a4cad9cSEnric Balletbo i Serra------------
59*0a4cad9cSEnric Balletbo i SerraAn integer containing the switch positions as bitfields:
60*0a4cad9cSEnric Balletbo i Serra
61*0a4cad9cSEnric Balletbo i Serra.. flat-table::
62*0a4cad9cSEnric Balletbo i Serra   :widths: 1 2
63*0a4cad9cSEnric Balletbo i Serra
64*0a4cad9cSEnric Balletbo i Serra   * - 0x00000002
65*0a4cad9cSEnric Balletbo i Serra     - Recovery button was pressed when x86 firmware booted.
66*0a4cad9cSEnric Balletbo i Serra
67*0a4cad9cSEnric Balletbo i Serra   * - 0x00000004
68*0a4cad9cSEnric Balletbo i Serra     - Recovery button was pressed when EC firmware booted. (required if EC EEPROM is
69*0a4cad9cSEnric Balletbo i Serra       rewritable; otherwise optional)
70*0a4cad9cSEnric Balletbo i Serra
71*0a4cad9cSEnric Balletbo i Serra   * - 0x00000020
72*0a4cad9cSEnric Balletbo i Serra     - Developer switch was enabled when x86 firmware booted.
73*0a4cad9cSEnric Balletbo i Serra
74*0a4cad9cSEnric Balletbo i Serra   * - 0x00000200
75*0a4cad9cSEnric Balletbo i Serra     - Firmware write protection was disabled when x86 firmware booted. (required if
76*0a4cad9cSEnric Balletbo i Serra       firmware write protection is controlled through x86 BIOS; otherwise optional)
77*0a4cad9cSEnric Balletbo i Serra
78*0a4cad9cSEnric Balletbo i SerraAll other bits are reserved and should be set to 0.
79*0a4cad9cSEnric Balletbo i Serra
80*0a4cad9cSEnric Balletbo i SerraHWID (Chrome OS hardware ID)
81*0a4cad9cSEnric Balletbo i Serra============================
82*0a4cad9cSEnric Balletbo i SerraThis control method returns the hardware ID for the Chromebook.
83*0a4cad9cSEnric Balletbo i Serra
84*0a4cad9cSEnric Balletbo i SerraArguments:
85*0a4cad9cSEnric Balletbo i Serra----------
86*0a4cad9cSEnric Balletbo i SerraNone
87*0a4cad9cSEnric Balletbo i Serra
88*0a4cad9cSEnric Balletbo i SerraResult code:
89*0a4cad9cSEnric Balletbo i Serra------------
90*0a4cad9cSEnric Balletbo i SerraA null-terminated ASCII string containing the hardware ID from the Model-Specific Data area of
91*0a4cad9cSEnric Balletbo i SerraEEPROM.
92*0a4cad9cSEnric Balletbo i Serra
93*0a4cad9cSEnric Balletbo i SerraNote that the hardware ID can be up to 256 characters long, including the terminating null.
94*0a4cad9cSEnric Balletbo i Serra
95*0a4cad9cSEnric Balletbo i SerraFWID (Chrome OS firmware version)
96*0a4cad9cSEnric Balletbo i Serra=================================
97*0a4cad9cSEnric Balletbo i SerraThis control method returns the firmware version for the rewritable portion of the main
98*0a4cad9cSEnric Balletbo i Serraprocessor firmware.
99*0a4cad9cSEnric Balletbo i Serra
100*0a4cad9cSEnric Balletbo i SerraArguments:
101*0a4cad9cSEnric Balletbo i Serra----------
102*0a4cad9cSEnric Balletbo i SerraNone
103*0a4cad9cSEnric Balletbo i Serra
104*0a4cad9cSEnric Balletbo i SerraResult code:
105*0a4cad9cSEnric Balletbo i Serra------------
106*0a4cad9cSEnric Balletbo i SerraA null-terminated ASCII string containing the complete firmware version for the rewritable
107*0a4cad9cSEnric Balletbo i Serraportion of the main processor firmware.
108*0a4cad9cSEnric Balletbo i Serra
109*0a4cad9cSEnric Balletbo i SerraFRID (Chrome OS read-only firmware version)
110*0a4cad9cSEnric Balletbo i Serra===========================================
111*0a4cad9cSEnric Balletbo i SerraThis control method returns the firmware version for the read-only portion of the main
112*0a4cad9cSEnric Balletbo i Serraprocessor firmware.
113*0a4cad9cSEnric Balletbo i Serra
114*0a4cad9cSEnric Balletbo i SerraArguments:
115*0a4cad9cSEnric Balletbo i Serra----------
116*0a4cad9cSEnric Balletbo i SerraNone
117*0a4cad9cSEnric Balletbo i Serra
118*0a4cad9cSEnric Balletbo i SerraResult code:
119*0a4cad9cSEnric Balletbo i Serra------------
120*0a4cad9cSEnric Balletbo i SerraA null-terminated ASCII string containing the complete firmware version for the read-only
121*0a4cad9cSEnric Balletbo i Serra(bootstrap + recovery ) portion of the main processor firmware.
122*0a4cad9cSEnric Balletbo i Serra
123*0a4cad9cSEnric Balletbo i SerraBINF (Chrome OS boot information)
124*0a4cad9cSEnric Balletbo i Serra=================================
125*0a4cad9cSEnric Balletbo i SerraThis control method returns information about the current boot.
126*0a4cad9cSEnric Balletbo i Serra
127*0a4cad9cSEnric Balletbo i SerraArguments:
128*0a4cad9cSEnric Balletbo i Serra----------
129*0a4cad9cSEnric Balletbo i SerraNone
130*0a4cad9cSEnric Balletbo i Serra
131*0a4cad9cSEnric Balletbo i SerraResult code:
132*0a4cad9cSEnric Balletbo i Serra------------
133*0a4cad9cSEnric Balletbo i Serra
134*0a4cad9cSEnric Balletbo i Serra.. code-block::
135*0a4cad9cSEnric Balletbo i Serra
136*0a4cad9cSEnric Balletbo i Serra   Package {
137*0a4cad9cSEnric Balletbo i Serra           Reserved1
138*0a4cad9cSEnric Balletbo i Serra           Reserved2
139*0a4cad9cSEnric Balletbo i Serra           Active EC Firmware
140*0a4cad9cSEnric Balletbo i Serra           Active Main Firmware Type
141*0a4cad9cSEnric Balletbo i Serra           Reserved5
142*0a4cad9cSEnric Balletbo i Serra   }
143*0a4cad9cSEnric Balletbo i Serra
144*0a4cad9cSEnric Balletbo i Serra.. flat-table::
145*0a4cad9cSEnric Balletbo i Serra   :widths: 1 1 2
146*0a4cad9cSEnric Balletbo i Serra   :header-rows: 1
147*0a4cad9cSEnric Balletbo i Serra
148*0a4cad9cSEnric Balletbo i Serra   * - Field
149*0a4cad9cSEnric Balletbo i Serra     - Format
150*0a4cad9cSEnric Balletbo i Serra     - Description
151*0a4cad9cSEnric Balletbo i Serra
152*0a4cad9cSEnric Balletbo i Serra   * - Reserved1
153*0a4cad9cSEnric Balletbo i Serra     - DWORD
154*0a4cad9cSEnric Balletbo i Serra     - Set to 256 (0x100). This indicates this field is no longer used.
155*0a4cad9cSEnric Balletbo i Serra
156*0a4cad9cSEnric Balletbo i Serra   * - Reserved2
157*0a4cad9cSEnric Balletbo i Serra     - DWORD
158*0a4cad9cSEnric Balletbo i Serra     - Set to 256 (0x100). This indicates this field is no longer used.
159*0a4cad9cSEnric Balletbo i Serra
160*0a4cad9cSEnric Balletbo i Serra   * - Active EC firmware
161*0a4cad9cSEnric Balletbo i Serra     - DWORD
162*0a4cad9cSEnric Balletbo i Serra     - The EC firmware which was used during boot.
163*0a4cad9cSEnric Balletbo i Serra
164*0a4cad9cSEnric Balletbo i Serra       - 0 - Read-only (recovery) firmware
165*0a4cad9cSEnric Balletbo i Serra       - 1 - Rewritable firmware.
166*0a4cad9cSEnric Balletbo i Serra
167*0a4cad9cSEnric Balletbo i Serra       Set to 0 if EC firmware is always read-only.
168*0a4cad9cSEnric Balletbo i Serra
169*0a4cad9cSEnric Balletbo i Serra   * - Active Main Firmware Type
170*0a4cad9cSEnric Balletbo i Serra     - DWORD
171*0a4cad9cSEnric Balletbo i Serra     - The main firmware type which was used during boot.
172*0a4cad9cSEnric Balletbo i Serra
173*0a4cad9cSEnric Balletbo i Serra       - 0 - Recovery
174*0a4cad9cSEnric Balletbo i Serra       - 1 - Normal
175*0a4cad9cSEnric Balletbo i Serra       - 2 - Developer
176*0a4cad9cSEnric Balletbo i Serra       - 3 - netboot (factory installation only)
177*0a4cad9cSEnric Balletbo i Serra
178*0a4cad9cSEnric Balletbo i Serra       Other values are reserved.
179*0a4cad9cSEnric Balletbo i Serra
180*0a4cad9cSEnric Balletbo i Serra   * - Reserved5
181*0a4cad9cSEnric Balletbo i Serra     - DWORD
182*0a4cad9cSEnric Balletbo i Serra     - Set to 256 (0x100). This indicates this field is no longer used.
183*0a4cad9cSEnric Balletbo i Serra
184*0a4cad9cSEnric Balletbo i SerraGPIO (Chrome OS GPIO assignments)
185*0a4cad9cSEnric Balletbo i Serra=================================
186*0a4cad9cSEnric Balletbo i SerraThis control method returns information about Chrome OS specific GPIO assignments for
187*0a4cad9cSEnric Balletbo i SerraChrome OS hardware, so the kernel can directly control that hardware.
188*0a4cad9cSEnric Balletbo i Serra
189*0a4cad9cSEnric Balletbo i SerraArguments:
190*0a4cad9cSEnric Balletbo i Serra----------
191*0a4cad9cSEnric Balletbo i SerraNone
192*0a4cad9cSEnric Balletbo i Serra
193*0a4cad9cSEnric Balletbo i SerraResult code:
194*0a4cad9cSEnric Balletbo i Serra------------
195*0a4cad9cSEnric Balletbo i Serra.. code-block::
196*0a4cad9cSEnric Balletbo i Serra
197*0a4cad9cSEnric Balletbo i Serra        Package {
198*0a4cad9cSEnric Balletbo i Serra                Package {
199*0a4cad9cSEnric Balletbo i Serra                        // First GPIO assignment
200*0a4cad9cSEnric Balletbo i Serra                        Signal Type        //DWORD
201*0a4cad9cSEnric Balletbo i Serra                        Attributes         //DWORD
202*0a4cad9cSEnric Balletbo i Serra                        Controller Offset  //DWORD
203*0a4cad9cSEnric Balletbo i Serra                        Controller Name    //ASCIIZ
204*0a4cad9cSEnric Balletbo i Serra                },
205*0a4cad9cSEnric Balletbo i Serra                ...
206*0a4cad9cSEnric Balletbo i Serra                Package {
207*0a4cad9cSEnric Balletbo i Serra                        // Last GPIO assignment
208*0a4cad9cSEnric Balletbo i Serra                        Signal Type        //DWORD
209*0a4cad9cSEnric Balletbo i Serra                        Attributes         //DWORD
210*0a4cad9cSEnric Balletbo i Serra                        Controller Offset  //DWORD
211*0a4cad9cSEnric Balletbo i Serra                        Controller Name    //ASCIIZ
212*0a4cad9cSEnric Balletbo i Serra                }
213*0a4cad9cSEnric Balletbo i Serra        }
214*0a4cad9cSEnric Balletbo i Serra
215*0a4cad9cSEnric Balletbo i SerraWhere ASCIIZ means a null-terminated ASCII string.
216*0a4cad9cSEnric Balletbo i Serra
217*0a4cad9cSEnric Balletbo i Serra.. flat-table::
218*0a4cad9cSEnric Balletbo i Serra   :widths: 1 1 2
219*0a4cad9cSEnric Balletbo i Serra   :header-rows: 1
220*0a4cad9cSEnric Balletbo i Serra
221*0a4cad9cSEnric Balletbo i Serra   * - Field
222*0a4cad9cSEnric Balletbo i Serra     - Format
223*0a4cad9cSEnric Balletbo i Serra     - Description
224*0a4cad9cSEnric Balletbo i Serra
225*0a4cad9cSEnric Balletbo i Serra   * - Signal Type
226*0a4cad9cSEnric Balletbo i Serra     - DWORD
227*0a4cad9cSEnric Balletbo i Serra     - Type of GPIO signal
228*0a4cad9cSEnric Balletbo i Serra
229*0a4cad9cSEnric Balletbo i Serra       - 0x00000001 - Recovery button
230*0a4cad9cSEnric Balletbo i Serra       - 0x00000002 - Developer mode switch
231*0a4cad9cSEnric Balletbo i Serra       - 0x00000003 - Firmware write protection switch
232*0a4cad9cSEnric Balletbo i Serra       - 0x00000100 - Debug header GPIO 0
233*0a4cad9cSEnric Balletbo i Serra       - ...
234*0a4cad9cSEnric Balletbo i Serra       - 0x000001FF - Debug header GPIO 255
235*0a4cad9cSEnric Balletbo i Serra
236*0a4cad9cSEnric Balletbo i Serra       Other values are reserved.
237*0a4cad9cSEnric Balletbo i Serra
238*0a4cad9cSEnric Balletbo i Serra   * - Attributes
239*0a4cad9cSEnric Balletbo i Serra     - DWORD
240*0a4cad9cSEnric Balletbo i Serra     - Signal attributes as bitfields:
241*0a4cad9cSEnric Balletbo i Serra
242*0a4cad9cSEnric Balletbo i Serra       - 0x00000001 - Signal is active-high (for button, a GPIO value
243*0a4cad9cSEnric Balletbo i Serra         of 1 means the button is pressed; for switches, a GPIO value
244*0a4cad9cSEnric Balletbo i Serra         of 1 means the switch is enabled). If this bit is 0, the signal
245*0a4cad9cSEnric Balletbo i Serra         is active low. Set to 0 for debug header GPIOs.
246*0a4cad9cSEnric Balletbo i Serra
247*0a4cad9cSEnric Balletbo i Serra   * - Controller Offset
248*0a4cad9cSEnric Balletbo i Serra     - DWORD
249*0a4cad9cSEnric Balletbo i Serra     - GPIO number on the specified controller.
250*0a4cad9cSEnric Balletbo i Serra
251*0a4cad9cSEnric Balletbo i Serra   * - Controller Name
252*0a4cad9cSEnric Balletbo i Serra     - ASCIIZ
253*0a4cad9cSEnric Balletbo i Serra     - Name of the controller for the GPIO.
254*0a4cad9cSEnric Balletbo i Serra       Currently supported names:
255*0a4cad9cSEnric Balletbo i Serra       "NM10" - Intel NM10 chip
256*0a4cad9cSEnric Balletbo i Serra
257*0a4cad9cSEnric Balletbo i SerraVBNV (Chrome OS NVRAM locations)
258*0a4cad9cSEnric Balletbo i Serra================================
259*0a4cad9cSEnric Balletbo i SerraThis control method returns information about the NVRAM (CMOS) locations used to
260*0a4cad9cSEnric Balletbo i Serracommunicate with the BIOS.
261*0a4cad9cSEnric Balletbo i Serra
262*0a4cad9cSEnric Balletbo i SerraArguments:
263*0a4cad9cSEnric Balletbo i Serra----------
264*0a4cad9cSEnric Balletbo i SerraNone
265*0a4cad9cSEnric Balletbo i Serra
266*0a4cad9cSEnric Balletbo i SerraResult code:
267*0a4cad9cSEnric Balletbo i Serra------------
268*0a4cad9cSEnric Balletbo i Serra.. code-block::
269*0a4cad9cSEnric Balletbo i Serra
270*0a4cad9cSEnric Balletbo i Serra        Package {
271*0a4cad9cSEnric Balletbo i Serra                NV Storage Block Offset  //DWORD
272*0a4cad9cSEnric Balletbo i Serra                NV Storage Block Size    //DWORD
273*0a4cad9cSEnric Balletbo i Serra        }
274*0a4cad9cSEnric Balletbo i Serra
275*0a4cad9cSEnric Balletbo i Serra.. flat-table::
276*0a4cad9cSEnric Balletbo i Serra   :widths: 1 1 2
277*0a4cad9cSEnric Balletbo i Serra   :header-rows: 1
278*0a4cad9cSEnric Balletbo i Serra
279*0a4cad9cSEnric Balletbo i Serra   * - Field
280*0a4cad9cSEnric Balletbo i Serra     - Format
281*0a4cad9cSEnric Balletbo i Serra     - Description
282*0a4cad9cSEnric Balletbo i Serra
283*0a4cad9cSEnric Balletbo i Serra   * - NV Storage Block Offset
284*0a4cad9cSEnric Balletbo i Serra     - DWORD
285*0a4cad9cSEnric Balletbo i Serra     - Offset in CMOS bank 0 of the verified boot non-volatile storage block, counting from
286*0a4cad9cSEnric Balletbo i Serra       the first writable CMOS byte (that is, offset=0 is the byte following the 14 bytes of
287*0a4cad9cSEnric Balletbo i Serra       clock data).
288*0a4cad9cSEnric Balletbo i Serra
289*0a4cad9cSEnric Balletbo i Serra   * - NV Storage Block Size
290*0a4cad9cSEnric Balletbo i Serra     - DWORD
291*0a4cad9cSEnric Balletbo i Serra     - Size in bytes of the verified boot non-volatile storage block.
292*0a4cad9cSEnric Balletbo i Serra
293*0a4cad9cSEnric Balletbo i SerraFMAP (Chrome OS flashmap address)
294*0a4cad9cSEnric Balletbo i Serra=================================
295*0a4cad9cSEnric Balletbo i SerraThis control method returns the physical memory address of the start of the main processor
296*0a4cad9cSEnric Balletbo i Serrafirmware flashmap.
297*0a4cad9cSEnric Balletbo i Serra
298*0a4cad9cSEnric Balletbo i SerraArguments:
299*0a4cad9cSEnric Balletbo i Serra----------
300*0a4cad9cSEnric Balletbo i SerraNone
301*0a4cad9cSEnric Balletbo i Serra
302*0a4cad9cSEnric Balletbo i SerraNoneResult code:
303*0a4cad9cSEnric Balletbo i Serra----------------
304*0a4cad9cSEnric Balletbo i SerraA DWORD containing the physical memory address of the start of the main processor firmware
305*0a4cad9cSEnric Balletbo i Serraflashmap.
306*0a4cad9cSEnric Balletbo i Serra
307*0a4cad9cSEnric Balletbo i SerraVDTA (Chrome OS verified boot data)
308*0a4cad9cSEnric Balletbo i Serra===================================
309*0a4cad9cSEnric Balletbo i SerraThis control method returns the verified boot data block shared between the firmware
310*0a4cad9cSEnric Balletbo i Serraverification step and the kernel verification step.
311*0a4cad9cSEnric Balletbo i Serra
312*0a4cad9cSEnric Balletbo i SerraArguments:
313*0a4cad9cSEnric Balletbo i Serra----------
314*0a4cad9cSEnric Balletbo i SerraNone
315*0a4cad9cSEnric Balletbo i Serra
316*0a4cad9cSEnric Balletbo i SerraResult code:
317*0a4cad9cSEnric Balletbo i Serra------------
318*0a4cad9cSEnric Balletbo i SerraA buffer containing the verified boot data block.
319*0a4cad9cSEnric Balletbo i Serra
320*0a4cad9cSEnric Balletbo i SerraMECK (Management Engine Checksum)
321*0a4cad9cSEnric Balletbo i Serra=================================
322*0a4cad9cSEnric Balletbo i SerraThis control method returns the SHA-1 or SHA-256 hash that is read out of the Management
323*0a4cad9cSEnric Balletbo i SerraEngine extended registers during boot. The hash is exported via ACPI so the OS can verify that
324*0a4cad9cSEnric Balletbo i Serrathe ME firmware has not changed. If Management Engine is not present, or if the firmware was
325*0a4cad9cSEnric Balletbo i Serraunable to read the extended registers, this buffer can be zero.
326*0a4cad9cSEnric Balletbo i Serra
327*0a4cad9cSEnric Balletbo i SerraArguments:
328*0a4cad9cSEnric Balletbo i Serra----------
329*0a4cad9cSEnric Balletbo i SerraNone
330*0a4cad9cSEnric Balletbo i Serra
331*0a4cad9cSEnric Balletbo i SerraResult code:
332*0a4cad9cSEnric Balletbo i Serra------------
333*0a4cad9cSEnric Balletbo i SerraA buffer containing the ME hash.
334*0a4cad9cSEnric Balletbo i Serra
335*0a4cad9cSEnric Balletbo i SerraMLST (Chrome OS method list)
336*0a4cad9cSEnric Balletbo i Serra============================
337*0a4cad9cSEnric Balletbo i SerraThis control method returns a list of the other control methods supported by the Chrome OS
338*0a4cad9cSEnric Balletbo i Serrahardware device.
339*0a4cad9cSEnric Balletbo i Serra
340*0a4cad9cSEnric Balletbo i SerraArguments:
341*0a4cad9cSEnric Balletbo i Serra----------
342*0a4cad9cSEnric Balletbo i SerraNone
343*0a4cad9cSEnric Balletbo i Serra
344*0a4cad9cSEnric Balletbo i SerraResult code:
345*0a4cad9cSEnric Balletbo i Serra------------
346*0a4cad9cSEnric Balletbo i SerraA package containing a list of null-terminated ASCII strings, one for each control method
347*0a4cad9cSEnric Balletbo i Serrasupported by the Chrome OS hardware device, not including the MLST method itself.
348*0a4cad9cSEnric Balletbo i SerraFor this version of the specification, the result is:
349*0a4cad9cSEnric Balletbo i Serra
350*0a4cad9cSEnric Balletbo i Serra.. code-block::
351*0a4cad9cSEnric Balletbo i Serra
352*0a4cad9cSEnric Balletbo i Serra        Package {
353*0a4cad9cSEnric Balletbo i Serra                "CHSW",
354*0a4cad9cSEnric Balletbo i Serra                "FWID",
355*0a4cad9cSEnric Balletbo i Serra                "HWID",
356*0a4cad9cSEnric Balletbo i Serra                "FRID",
357*0a4cad9cSEnric Balletbo i Serra                "BINF",
358*0a4cad9cSEnric Balletbo i Serra                "GPIO",
359*0a4cad9cSEnric Balletbo i Serra                "VBNV",
360*0a4cad9cSEnric Balletbo i Serra                "FMAP",
361*0a4cad9cSEnric Balletbo i Serra                "VDTA",
362*0a4cad9cSEnric Balletbo i Serra                "MECK"
363*0a4cad9cSEnric Balletbo i Serra        }
364