1========================= 2Audio Stream in SoundWire 3========================= 4 5An audio stream is a logical or virtual connection created between 6 7 (1) System memory buffer(s) and Codec(s) 8 9 (2) DSP memory buffer(s) and Codec(s) 10 11 (3) FIFO(s) and Codec(s) 12 13 (4) Codec(s) and Codec(s) 14 15which is typically driven by a DMA(s) channel through the data link. An 16audio stream contains one or more channels of data. All channels within 17stream must have same sample rate and same sample size. 18 19Assume a stream with two channels (Left & Right) is opened using SoundWire 20interface. Below are some ways a stream can be represented in SoundWire. 21 22Stream Sample in memory (System memory, DSP memory or FIFOs) :: 23 24 ------------------------- 25 | L | R | L | R | L | R | 26 ------------------------- 27 28Example 1: Stereo Stream with L and R channels is rendered from Master to 29Slave. Both Master and Slave is using single port. :: 30 31 +---------------+ Clock Signal +---------------+ 32 | Master +----------------------------------+ Slave | 33 | Interface | | Interface | 34 | | | 1 | 35 | | Data Signal | | 36 | L + R +----------------------------------+ L + R | 37 | (Data) | Data Direction | (Data) | 38 +---------------+ +-----------------------> +---------------+ 39 40 41Example 2: Stereo Stream with L and R channels is captured from Slave to 42Master. Both Master and Slave is using single port. :: 43 44 45 +---------------+ Clock Signal +---------------+ 46 | Master +----------------------------------+ Slave | 47 | Interface | | Interface | 48 | | | 1 | 49 | | Data Signal | | 50 | L + R +----------------------------------+ L + R | 51 | (Data) | Data Direction | (Data) | 52 +---------------+ <-----------------------+ +---------------+ 53 54 55Example 3: Stereo Stream with L and R channels is rendered by Master. Each 56of the L and R channel is received by two different Slaves. Master and both 57Slaves are using single port. :: 58 59 +---------------+ Clock Signal +---------------+ 60 | Master +---------+------------------------+ Slave | 61 | Interface | | | Interface | 62 | | | | 1 | 63 | | | Data Signal | | 64 | L + R +---+------------------------------+ L | 65 | (Data) | | | Data Direction | (Data) | 66 +---------------+ | | +-------------> +---------------+ 67 | | 68 | | 69 | | +---------------+ 70 | +----------------------> | Slave | 71 | | Interface | 72 | | 2 | 73 | | | 74 +----------------------------> | R | 75 | (Data) | 76 +---------------+ 77 78 79Example 4: Stereo Stream with L and R channel is rendered by two different 80Ports of the Master and is received by only single Port of the Slave 81interface. :: 82 83 +--------------------+ 84 | | 85 | +--------------+ +----------------+ 86 | | || | | 87 | | Data Port || L Channel | | 88 | | 1 |------------+ | | 89 | | L Channel || | +-----+----+ | 90 | | (Data) || | L + R Channel || Data | | 91 | Master +----------+ | +---+---------> || Port | | 92 | Interface | | || 1 | | 93 | +--------------+ | || | | 94 | | || | +----------+ | 95 | | Data Port |------------+ | | 96 | | 2 || R Channel | Slave | 97 | | R Channel || | Interface | 98 | | (Data) || | 1 | 99 | +--------------+ Clock Signal | L + R | 100 | +---------------------------> | (Data) | 101 +--------------------+ | | 102 +----------------+ 103 104Example 5: Stereo Stream with L and R channel is rendered by 2 Masters, each 105rendering one channel, and is received by two different Slaves, each 106receiving one channel. Both Masters and both Slaves are using single port. :: 107 108 +---------------+ Clock Signal +---------------+ 109 | Master +----------------------------------+ Slave | 110 | Interface | | Interface | 111 | 1 | | 1 | 112 | | Data Signal | | 113 | L +----------------------------------+ L | 114 | (Data) | Data Direction | (Data) | 115 +---------------+ +-----------------------> +---------------+ 116 117 +---------------+ Clock Signal +---------------+ 118 | Master +----------------------------------+ Slave | 119 | Interface | | Interface | 120 | 2 | | 2 | 121 | | Data Signal | | 122 | R +----------------------------------+ R | 123 | (Data) | Data Direction | (Data) | 124 +---------------+ +-----------------------> +---------------+ 125 126Note: In multi-link cases like above, to lock, one would acquire a global 127lock and then go on locking bus instances. But, in this case the caller 128framework(ASoC DPCM) guarantees that stream operations on a card are 129always serialized. So, there is no race condition and hence no need for 130global lock. 131 132SoundWire Stream Management flow 133================================ 134 135Stream definitions 136------------------ 137 138 (1) Current stream: This is classified as the stream on which operation has 139 to be performed like prepare, enable, disable, de-prepare etc. 140 141 (2) Active stream: This is classified as the stream which is already active 142 on Bus other than current stream. There can be multiple active streams 143 on the Bus. 144 145SoundWire Bus manages stream operations for each stream getting 146rendered/captured on the SoundWire Bus. This section explains Bus operations 147done for each of the stream allocated/released on Bus. Following are the 148stream states maintained by the Bus for each of the audio stream. 149 150 151SoundWire stream states 152----------------------- 153 154Below shows the SoundWire stream states and state transition diagram. :: 155 156 +-----------+ +------------+ +----------+ +----------+ 157 | ALLOCATED +---->| CONFIGURED +---->| PREPARED +---->| ENABLED | 158 | STATE | | STATE | | STATE | | STATE | 159 +-----------+ +------------+ +---+--+---+ +----+-----+ 160 ^ ^ ^ 161 | | | 162 __| |___________ | 163 | | | 164 v | v 165 +----------+ +-----+------+ +-+--+-----+ 166 | RELEASED |<----------+ DEPREPARED |<-------+ DISABLED | 167 | STATE | | STATE | | STATE | 168 +----------+ +------------+ +----------+ 169 170NOTE: State transitions between ``SDW_STREAM_ENABLED`` and 171``SDW_STREAM_DISABLED`` are only relevant when then INFO_PAUSE flag is 172supported at the ALSA/ASoC level. Likewise the transition between 173``SDW_DISABLED_STATE`` and ``SDW_PREPARED_STATE`` depends on the 174INFO_RESUME flag. 175 176NOTE2: The framework implements basic state transition checks, but 177does not e.g. check if a transition from DISABLED to ENABLED is valid 178on a specific platform. Such tests need to be added at the ALSA/ASoC 179level. 180 181Stream State Operations 182----------------------- 183 184Below section explains the operations done by the Bus on Master(s) and 185Slave(s) as part of stream state transitions. 186 187SDW_STREAM_ALLOCATED 188~~~~~~~~~~~~~~~~~~~~ 189 190Allocation state for stream. This is the entry state 191of the stream. Operations performed before entering in this state: 192 193 (1) A stream runtime is allocated for the stream. This stream 194 runtime is used as a reference for all the operations performed 195 on the stream. 196 197 (2) The resources required for holding stream runtime information are 198 allocated and initialized. This holds all stream related information 199 such as stream type (PCM/PDM) and parameters, Master and Slave 200 interface associated with the stream, stream state etc. 201 202After all above operations are successful, stream state is set to 203``SDW_STREAM_ALLOCATED``. 204 205Bus implements below API for allocate a stream which needs to be called once 206per stream. From ASoC DPCM framework, this stream state maybe linked to 207.startup() operation. 208 209.. code-block:: c 210 211 int sdw_alloc_stream(char * stream_name); 212 213 214SDW_STREAM_CONFIGURED 215~~~~~~~~~~~~~~~~~~~~~ 216 217Configuration state of stream. Operations performed before entering in 218this state: 219 220 (1) The resources allocated for stream information in SDW_STREAM_ALLOCATED 221 state are updated here. This includes stream parameters, Master(s) 222 and Slave(s) runtime information associated with current stream. 223 224 (2) All the Master(s) and Slave(s) associated with current stream provide 225 the port information to Bus which includes port numbers allocated by 226 Master(s) and Slave(s) for current stream and their channel mask. 227 228After all above operations are successful, stream state is set to 229``SDW_STREAM_CONFIGURED``. 230 231Bus implements below APIs for CONFIG state which needs to be called by 232the respective Master(s) and Slave(s) associated with stream. These APIs can 233only be invoked once by respective Master(s) and Slave(s). From ASoC DPCM 234framework, this stream state is linked to .hw_params() operation. 235 236.. code-block:: c 237 238 int sdw_stream_add_master(struct sdw_bus * bus, 239 struct sdw_stream_config * stream_config, 240 struct sdw_ports_config * ports_config, 241 struct sdw_stream_runtime * stream); 242 243 int sdw_stream_add_slave(struct sdw_slave * slave, 244 struct sdw_stream_config * stream_config, 245 struct sdw_ports_config * ports_config, 246 struct sdw_stream_runtime * stream); 247 248 249SDW_STREAM_PREPARED 250~~~~~~~~~~~~~~~~~~~ 251 252Prepare state of stream. Operations performed before entering in this state: 253 254 (0) Steps 1 and 2 are omitted in the case of a resume operation, 255 where the bus bandwidth is known. 256 257 (1) Bus parameters such as bandwidth, frame shape, clock frequency, 258 are computed based on current stream as well as already active 259 stream(s) on Bus. Re-computation is required to accommodate current 260 stream on the Bus. 261 262 (2) Transport and port parameters of all Master(s) and Slave(s) port(s) are 263 computed for the current as well as already active stream based on frame 264 shape and clock frequency computed in step 1. 265 266 (3) Computed Bus and transport parameters are programmed in Master(s) and 267 Slave(s) registers. The banked registers programming is done on the 268 alternate bank (bank currently unused). Port(s) are enabled for the 269 already active stream(s) on the alternate bank (bank currently unused). 270 This is done in order to not disrupt already active stream(s). 271 272 (4) Once all the values are programmed, Bus initiates switch to alternate 273 bank where all new values programmed gets into effect. 274 275 (5) Ports of Master(s) and Slave(s) for current stream are prepared by 276 programming PrepareCtrl register. 277 278After all above operations are successful, stream state is set to 279``SDW_STREAM_PREPARED``. 280 281Bus implements below API for PREPARE state which needs to be called 282once per stream. From ASoC DPCM framework, this stream state is linked 283to .prepare() operation. Since the .trigger() operations may not 284follow the .prepare(), a direct transition from 285``SDW_STREAM_PREPARED`` to ``SDW_STREAM_DEPREPARED`` is allowed. 286 287.. code-block:: c 288 289 int sdw_prepare_stream(struct sdw_stream_runtime * stream); 290 291 292SDW_STREAM_ENABLED 293~~~~~~~~~~~~~~~~~~ 294 295Enable state of stream. The data port(s) are enabled upon entering this state. 296Operations performed before entering in this state: 297 298 (1) All the values computed in SDW_STREAM_PREPARED state are programmed 299 in alternate bank (bank currently unused). It includes programming of 300 already active stream(s) as well. 301 302 (2) All the Master(s) and Slave(s) port(s) for the current stream are 303 enabled on alternate bank (bank currently unused) by programming 304 ChannelEn register. 305 306 (3) Once all the values are programmed, Bus initiates switch to alternate 307 bank where all new values programmed gets into effect and port(s) 308 associated with current stream are enabled. 309 310After all above operations are successful, stream state is set to 311``SDW_STREAM_ENABLED``. 312 313Bus implements below API for ENABLE state which needs to be called once per 314stream. From ASoC DPCM framework, this stream state is linked to 315.trigger() start operation. 316 317.. code-block:: c 318 319 int sdw_enable_stream(struct sdw_stream_runtime * stream); 320 321SDW_STREAM_DISABLED 322~~~~~~~~~~~~~~~~~~~ 323 324Disable state of stream. The data port(s) are disabled upon exiting this state. 325Operations performed before entering in this state: 326 327 (1) All the Master(s) and Slave(s) port(s) for the current stream are 328 disabled on alternate bank (bank currently unused) by programming 329 ChannelEn register. 330 331 (2) All the current configuration of Bus and active stream(s) are programmed 332 into alternate bank (bank currently unused). 333 334 (3) Once all the values are programmed, Bus initiates switch to alternate 335 bank where all new values programmed gets into effect and port(s) associated 336 with current stream are disabled. 337 338After all above operations are successful, stream state is set to 339``SDW_STREAM_DISABLED``. 340 341Bus implements below API for DISABLED state which needs to be called once 342per stream. From ASoC DPCM framework, this stream state is linked to 343.trigger() stop operation. 344 345When the INFO_PAUSE flag is supported, a direct transition to 346``SDW_STREAM_ENABLED`` is allowed. 347 348For resume operations where ASoC will use the .prepare() callback, the 349stream can transition from ``SDW_STREAM_DISABLED`` to 350``SDW_STREAM_PREPARED``, with all required settings restored but 351without updating the bandwidth and bit allocation. 352 353.. code-block:: c 354 355 int sdw_disable_stream(struct sdw_stream_runtime * stream); 356 357 358SDW_STREAM_DEPREPARED 359~~~~~~~~~~~~~~~~~~~~~ 360 361De-prepare state of stream. Operations performed before entering in this 362state: 363 364 (1) All the port(s) of Master(s) and Slave(s) for current stream are 365 de-prepared by programming PrepareCtrl register. 366 367 (2) The payload bandwidth of current stream is reduced from the total 368 bandwidth requirement of bus and new parameters calculated and 369 applied by performing bank switch etc. 370 371After all above operations are successful, stream state is set to 372``SDW_STREAM_DEPREPARED``. 373 374Bus implements below API for DEPREPARED state which needs to be called 375once per stream. ALSA/ASoC do not have a concept of 'deprepare', and 376the mapping from this stream state to ALSA/ASoC operation may be 377implementation specific. 378 379When the INFO_PAUSE flag is supported, the stream state is linked to 380the .hw_free() operation - the stream is not deprepared on a 381TRIGGER_STOP. 382 383Other implementations may transition to the ``SDW_STREAM_DEPREPARED`` 384state on TRIGGER_STOP, should they require a transition through the 385``SDW_STREAM_PREPARED`` state. 386 387.. code-block:: c 388 389 int sdw_deprepare_stream(struct sdw_stream_runtime * stream); 390 391 392SDW_STREAM_RELEASED 393~~~~~~~~~~~~~~~~~~~ 394 395Release state of stream. Operations performed before entering in this state: 396 397 (1) Release port resources for all Master(s) and Slave(s) port(s) 398 associated with current stream. 399 400 (2) Release Master(s) and Slave(s) runtime resources associated with 401 current stream. 402 403 (3) Release stream runtime resources associated with current stream. 404 405After all above operations are successful, stream state is set to 406``SDW_STREAM_RELEASED``. 407 408Bus implements below APIs for RELEASE state which needs to be called by 409all the Master(s) and Slave(s) associated with stream. From ASoC DPCM 410framework, this stream state is linked to .hw_free() operation. 411 412.. code-block:: c 413 414 int sdw_stream_remove_master(struct sdw_bus * bus, 415 struct sdw_stream_runtime * stream); 416 int sdw_stream_remove_slave(struct sdw_slave * slave, 417 struct sdw_stream_runtime * stream); 418 419 420The .shutdown() ASoC DPCM operation calls below Bus API to release 421stream assigned as part of ALLOCATED state. 422 423In .shutdown() the data structure maintaining stream state are freed up. 424 425.. code-block:: c 426 427 void sdw_release_stream(struct sdw_stream_runtime * stream); 428 429Not Supported 430============= 431 4321. A single port with multiple channels supported cannot be used between two 433streams or across stream. For example a port with 4 channels cannot be used 434to handle 2 independent stereo streams even though it's possible in theory 435in SoundWire. 436