1.. SPDX-License-Identifier: GPL-2.0 2 3======================================== 4GPMC (General Purpose Memory Controller) 5======================================== 6 7GPMC is an unified memory controller dedicated to interfacing external 8memory devices like 9 10 * Asynchronous SRAM like memories and application specific integrated 11 circuit devices. 12 * Asynchronous, synchronous, and page mode burst NOR flash devices 13 NAND flash 14 * Pseudo-SRAM devices 15 16GPMC is found on Texas Instruments SoC's (OMAP based) 17IP details: https://www.ti.com/lit/pdf/spruh73 section 7.1 18 19 20GPMC generic timing calculation: 21================================ 22 23GPMC has certain timings that has to be programmed for proper 24functioning of the peripheral, while peripheral has another set of 25timings. To have peripheral work with gpmc, peripheral timings has to 26be translated to the form gpmc can understand. The way it has to be 27translated depends on the connected peripheral. Also there is a 28dependency for certain gpmc timings on gpmc clock frequency. Hence a 29generic timing routine was developed to achieve above requirements. 30 31Generic routine provides a generic method to calculate gpmc timings 32from gpmc peripheral timings. struct gpmc_device_timings fields has to 33be updated with timings from the datasheet of the peripheral that is 34connected to gpmc. A few of the peripheral timings can be fed either 35in time or in cycles, provision to handle this scenario has been 36provided (refer struct gpmc_device_timings definition). It may so 37happen that timing as specified by peripheral datasheet is not present 38in timing structure, in this scenario, try to correlate peripheral 39timing to the one available. If that doesn't work, try to add a new 40field as required by peripheral, educate generic timing routine to 41handle it, make sure that it does not break any of the existing. 42Then there may be cases where peripheral datasheet doesn't mention 43certain fields of struct gpmc_device_timings, zero those entries. 44 45Generic timing routine has been verified to work properly on 46multiple onenand's and tusb6010 peripherals. 47 48A word of caution: generic timing routine has been developed based 49on understanding of gpmc timings, peripheral timings, available 50custom timing routines, a kind of reverse engineering without 51most of the datasheets & hardware (to be exact none of those supported 52in mainline having custom timing routine) and by simulation. 53 54gpmc timing dependency on peripheral timings: 55 56[<gpmc_timing>: <peripheral timing1>, <peripheral timing2> ...] 57 581. common 59 60cs_on: 61 t_ceasu 62adv_on: 63 t_avdasu, t_ceavd 64 652. sync common 66 67sync_clk: 68 clk 69page_burst_access: 70 t_bacc 71clk_activation: 72 t_ces, t_avds 73 743. read async muxed 75 76adv_rd_off: 77 t_avdp_r 78oe_on: 79 t_oeasu, t_aavdh 80access: 81 t_iaa, t_oe, t_ce, t_aa 82rd_cycle: 83 t_rd_cycle, t_cez_r, t_oez 84 854. read async non-muxed 86 87adv_rd_off: 88 t_avdp_r 89oe_on: 90 t_oeasu 91access: 92 t_iaa, t_oe, t_ce, t_aa 93rd_cycle: 94 t_rd_cycle, t_cez_r, t_oez 95 965. read sync muxed 97 98adv_rd_off: 99 t_avdp_r, t_avdh 100oe_on: 101 t_oeasu, t_ach, cyc_aavdh_oe 102access: 103 t_iaa, cyc_iaa, cyc_oe 104rd_cycle: 105 t_cez_r, t_oez, t_ce_rdyz 106 1076. read sync non-muxed 108 109adv_rd_off: 110 t_avdp_r 111oe_on: 112 t_oeasu 113access: 114 t_iaa, cyc_iaa, cyc_oe 115rd_cycle: 116 t_cez_r, t_oez, t_ce_rdyz 117 1187. write async muxed 119 120adv_wr_off: 121 t_avdp_w 122we_on, wr_data_mux_bus: 123 t_weasu, t_aavdh, cyc_aavhd_we 124we_off: 125 t_wpl 126cs_wr_off: 127 t_wph 128wr_cycle: 129 t_cez_w, t_wr_cycle 130 1318. write async non-muxed 132 133adv_wr_off: 134 t_avdp_w 135we_on, wr_data_mux_bus: 136 t_weasu 137we_off: 138 t_wpl 139cs_wr_off: 140 t_wph 141wr_cycle: 142 t_cez_w, t_wr_cycle 143 1449. write sync muxed 145 146adv_wr_off: 147 t_avdp_w, t_avdh 148we_on, wr_data_mux_bus: 149 t_weasu, t_rdyo, t_aavdh, cyc_aavhd_we 150we_off: 151 t_wpl, cyc_wpl 152cs_wr_off: 153 t_wph 154wr_cycle: 155 t_cez_w, t_ce_rdyz 156 15710. write sync non-muxed 158 159adv_wr_off: 160 t_avdp_w 161we_on, wr_data_mux_bus: 162 t_weasu, t_rdyo 163we_off: 164 t_wpl, cyc_wpl 165cs_wr_off: 166 t_wph 167wr_cycle: 168 t_cez_w, t_ce_rdyz 169 170 171Note: 172 Many of gpmc timings are dependent on other gpmc timings (a few 173 gpmc timings purely dependent on other gpmc timings, a reason that 174 some of the gpmc timings are missing above), and it will result in 175 indirect dependency of peripheral timings to gpmc timings other than 176 mentioned above, refer timing routine for more details. To know what 177 these peripheral timings correspond to, please see explanations in 178 struct gpmc_device_timings definition. And for gpmc timings refer 179 IP details (link above). 180