1.. SPDX-License-Identifier: GPL-2.0 2 3=============================== 4The Linux kernel dpll subsystem 5=============================== 6 7DPLL 8==== 9 10PLL - Phase Locked Loop is an electronic circuit which syntonizes clock 11signal of a device with an external clock signal. Effectively enabling 12device to run on the same clock signal beat as provided on a PLL input. 13 14DPLL - Digital Phase Locked Loop is an integrated circuit which in 15addition to plain PLL behavior incorporates a digital phase detector 16and may have digital divider in the loop. As a result, the frequency on 17DPLL's input and output may be configurable. 18 19Subsystem 20========= 21 22The main purpose of dpll subsystem is to provide general interface 23to configure devices that use any kind of Digital PLL and could use 24different sources of input signal to synchronize to, as well as 25different types of outputs. 26The main interface is NETLINK_GENERIC based protocol with an event 27monitoring multicast group defined. 28 29Device object 30============= 31 32Single dpll device object means single Digital PLL circuit and bunch of 33connected pins. 34It reports the supported modes of operation and current status to the 35user in response to the `do` request of netlink command 36``DPLL_CMD_DEVICE_GET`` and list of dplls registered in the subsystem 37with `dump` netlink request of the same command. 38Changing the configuration of dpll device is done with `do` request of 39netlink ``DPLL_CMD_DEVICE_SET`` command. 40A device handle is ``DPLL_A_ID``, it shall be provided to get or set 41configuration of particular device in the system. It can be obtained 42with a ``DPLL_CMD_DEVICE_GET`` `dump` request or 43a ``DPLL_CMD_DEVICE_ID_GET`` `do` request, where the one must provide 44attributes that result in single device match. 45 46Pin object 47========== 48 49A pin is amorphic object which represents either input or output, it 50could be internal component of the device, as well as externally 51connected. 52The number of pins per dpll vary, but usually multiple pins shall be 53provided for a single dpll device. 54Pin's properties, capabilities and status is provided to the user in 55response to `do` request of netlink ``DPLL_CMD_PIN_GET`` command. 56It is also possible to list all the pins that were registered in the 57system with `dump` request of ``DPLL_CMD_PIN_GET`` command. 58Configuration of a pin can be changed by `do` request of netlink 59``DPLL_CMD_PIN_SET`` command. 60Pin handle is a ``DPLL_A_PIN_ID``, it shall be provided to get or set 61configuration of particular pin in the system. It can be obtained with 62``DPLL_CMD_PIN_GET`` `dump` request or ``DPLL_CMD_PIN_ID_GET`` `do` 63request, where user provides attributes that result in single pin match. 64 65Pin selection 66============= 67 68In general, selected pin (the one which signal is driving the dpll 69device) can be obtained from ``DPLL_A_PIN_STATE`` attribute, and only 70one pin shall be in ``DPLL_PIN_STATE_CONNECTED`` state for any dpll 71device. 72 73Pin selection can be done either manually or automatically, depending 74on hardware capabilities and active dpll device work mode 75(``DPLL_A_MODE`` attribute). The consequence is that there are 76differences for each mode in terms of available pin states, as well as 77for the states the user can request for a dpll device. 78 79In manual mode (``DPLL_MODE_MANUAL``) the user can request or receive 80one of following pin states: 81 82- ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device 83- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll 84 device 85 86In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can request or 87receive one of following pin states: 88 89- ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid 90 input for automatic selection algorithm 91- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as 92 a valid input for automatic selection algorithm 93 94In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can only receive 95pin state ``DPLL_PIN_STATE_CONNECTED`` once automatic selection 96algorithm locks a dpll device with one of the inputs. 97 98Shared pins 99=========== 100 101A single pin object can be attached to multiple dpll devices. 102Then there are two groups of configuration knobs: 103 1041) Set on a pin - the configuration affects all dpll devices pin is 105 registered to (i.e., ``DPLL_A_PIN_FREQUENCY``), 1062) Set on a pin-dpll tuple - the configuration affects only selected 107 dpll device (i.e., ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE``, 108 ``DPLL_A_PIN_DIRECTION``). 109 110MUX-type pins 111============= 112 113A pin can be MUX-type, it aggregates child pins and serves as a pin 114multiplexer. One or more pins are registered with MUX-type instead of 115being directly registered to a dpll device. 116Pins registered with a MUX-type pin provide user with additional nested 117attribute ``DPLL_A_PIN_PARENT_PIN`` for each parent they were registered 118with. 119If a pin was registered with multiple parent pins, they behave like a 120multiple output multiplexer. In this case output of a 121``DPLL_CMD_PIN_GET`` would contain multiple pin-parent nested 122attributes with current state related to each parent, like:: 123 124 'pin': [{{ 125 'clock-id': 282574471561216, 126 'module-name': 'ice', 127 'capabilities': 4, 128 'id': 13, 129 'parent-pin': [ 130 {'parent-id': 2, 'state': 'connected'}, 131 {'parent-id': 3, 'state': 'disconnected'} 132 ], 133 'type': 'synce-eth-port' 134 }}] 135 136Only one child pin can provide its signal to the parent MUX-type pin at 137a time, the selection is done by requesting change of a child pin state 138on desired parent, with the use of ``DPLL_A_PIN_PARENT`` nested 139attribute. Example of netlink `set state on parent pin` message format: 140 141 ========================== ============================================= 142 ``DPLL_A_PIN_ID`` child pin id 143 ``DPLL_A_PIN_PARENT_PIN`` nested attribute for requesting configuration 144 related to parent pin 145 ``DPLL_A_PIN_PARENT_ID`` parent pin id 146 ``DPLL_A_PIN_STATE`` requested pin state on parent 147 ========================== ============================================= 148 149Pin priority 150============ 151 152Some devices might offer a capability of automatic pin selection mode 153(enum value ``DPLL_MODE_AUTOMATIC`` of ``DPLL_A_MODE`` attribute). 154Usually, automatic selection is performed on the hardware level, which 155means only pins directly connected to the dpll can be used for automatic 156input pin selection. 157In automatic selection mode, the user cannot manually select a input 158pin for the device, instead the user shall provide all directly 159connected pins with a priority ``DPLL_A_PIN_PRIO``, the device would 160pick a highest priority valid signal and use it to control the DPLL 161device. Example of netlink `set priority on parent pin` message format: 162 163 ============================ ============================================= 164 ``DPLL_A_PIN_ID`` configured pin id 165 ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting configuration 166 related to parent dpll device 167 ``DPLL_A_PIN_PARENT_ID`` parent dpll device id 168 ``DPLL_A_PIN_PRIO`` requested pin prio on parent dpll 169 ============================ ============================================= 170 171Child pin of MUX-type pin is not capable of automatic input pin selection, 172in order to configure active input of a MUX-type pin, the user needs to 173request desired pin state of the child pin on the parent pin, 174as described in the ``MUX-type pins`` chapter. 175 176Phase offset measurement and adjustment 177======================================== 178 179Device may provide ability to measure a phase difference between signals 180on a pin and its parent dpll device. If pin-dpll phase offset measurement 181is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET`` 182attribute for each parent dpll device. The reported phase offset may be 183computed as the average of prior values and the current measurement, using 184the following formula: 185 186.. math:: 187 curr\_avg = prev\_avg * \frac{2^N-1}{2^N} + new\_val * \frac{1}{2^N} 188 189where `curr_avg` is the current reported phase offset, `prev_avg` is the 190previously reported value, `new_val` is the current measurement, and `N` is 191the averaging factor. Configured averaging factor value is provided with 192``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attribute of a device and value change can 193be requested with the same attribute with ``DPLL_CMD_DEVICE_SET`` command. 194 195 ================================== ====================================== 196 ``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attr configured value of phase offset 197 averaging factor 198 ================================== ====================================== 199 200Device may also provide ability to adjust a signal phase on a pin. 201If pin phase adjustment is supported, minimal and maximal values and 202granularity that pin handle shall be provided to the user on 203``DPLL_CMD_PIN_GET`` respond with ``DPLL_A_PIN_PHASE_ADJUST_MIN``, 204``DPLL_A_PIN_PHASE_ADJUST_MAX`` and ``DPLL_A_PIN_PHASE_ADJUST_GRAN`` 205attributes. Configured phase adjust value is provided with 206``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be 207requested with the same attribute with ``DPLL_CMD_PIN_SET`` command. 208 209 ================================ ========================================== 210 ``DPLL_A_PIN_ID`` configured pin id 211 ``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attr granularity of phase adjustment value 212 ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment 213 ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment 214 ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase 215 adjustment on parent dpll device 216 ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting 217 configuration on given parent dpll 218 device 219 ``DPLL_A_PIN_PARENT_ID`` parent dpll device id 220 ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference 221 between a pin and parent dpll device 222 ================================ ========================================== 223 224All phase related values are provided in pico seconds, which represents 225time difference between signals phase. The negative value means that 226phase of signal on pin is earlier in time than dpll's signal. Positive 227value means that phase of signal on pin is later in time than signal of 228a dpll. 229 230Phase adjust (also min and max) values are integers, but measured phase 231offset values are fractional with 3-digit decimal places and shell be 232divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and 233modulo divided to get fractional part. 234 235Phase offset monitor 236==================== 237 238Phase offset measurement is typically performed against the current active 239source. However, some DPLL (Digital Phase-Locked Loop) devices may offer 240the capability to monitor phase offsets across all available inputs. 241The attribute and current feature state shall be included in the response 242message of the ``DPLL_CMD_DEVICE_GET`` command for supported DPLL devices. 243In such cases, users can also control the feature using the 244``DPLL_CMD_DEVICE_SET`` command by setting the ``enum dpll_feature_state`` 245values for the attribute. 246Once enabled the phase offset measurements for the input shall be returned 247in the ``DPLL_A_PIN_PHASE_OFFSET`` attribute. 248 249 =============================== ======================== 250 ``DPLL_A_PHASE_OFFSET_MONITOR`` attr state of a feature 251 =============================== ======================== 252 253Embedded SYNC 254============= 255 256Device may provide ability to use Embedded SYNC feature. It allows 257to embed additional SYNC signal into the base frequency of a pin - a one 258special pulse of base frequency signal every time SYNC signal pulse 259happens. The user can configure the frequency of Embedded SYNC. 260The Embedded SYNC capability is always related to a given base frequency 261and HW capabilities. The user is provided a range of Embedded SYNC 262frequencies supported, depending on current base frequency configured for 263the pin. 264 265 ========================================= ================================= 266 ``DPLL_A_PIN_ESYNC_FREQUENCY`` current Embedded SYNC frequency 267 ``DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED`` nest available Embedded SYNC 268 frequency ranges 269 ``DPLL_A_PIN_FREQUENCY_MIN`` attr minimum value of frequency 270 ``DPLL_A_PIN_FREQUENCY_MAX`` attr maximum value of frequency 271 ``DPLL_A_PIN_ESYNC_PULSE`` pulse type of Embedded SYNC 272 ========================================= ================================= 273 274Reference SYNC 275============== 276 277The device may support the Reference SYNC feature, which allows the combination 278of two inputs into a input pair. In this configuration, clock signals 279from both inputs are used to synchronize the DPLL device. The higher frequency 280signal is utilized for the loop bandwidth of the DPLL, while the lower frequency 281signal is used to syntonize the output signal of the DPLL device. This feature 282enables the provision of a high-quality loop bandwidth signal from an external 283source. 284 285A capable input provides a list of inputs that can be bound with to create 286Reference SYNC. To control this feature, the user must request a desired 287state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or 288``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. An input pin can be 289bound to only one other pin at any given time. 290 291 ============================== ========================================== 292 ``DPLL_A_PIN_REFERENCE_SYNC`` nested attribute for providing info or 293 requesting configuration of the Reference 294 SYNC feature 295 ``DPLL_A_PIN_ID`` target pin id for Reference SYNC feature 296 ``DPLL_A_PIN_STATE`` state of Reference SYNC connection 297 ============================== ========================================== 298 299Configuration commands group 300============================ 301 302Configuration commands are used to get information about registered 303dpll devices (and pins), as well as set configuration of device or pins. 304As dpll devices must be abstracted and reflect real hardware, 305there is no way to add new dpll device via netlink from user space and 306each device should be registered by its driver. 307 308All netlink commands require ``GENL_ADMIN_PERM``. This is to prevent 309any spamming/DoS from unauthorized userspace applications. 310 311List of netlink commands with possible attributes 312================================================= 313 314Constants identifying command types for dpll device uses a 315``DPLL_CMD_`` prefix and suffix according to command purpose. 316The dpll device related attributes use a ``DPLL_A_`` prefix and 317suffix according to attribute purpose. 318 319 ==================================== ================================= 320 ``DPLL_CMD_DEVICE_ID_GET`` command to get device ID 321 ``DPLL_A_MODULE_NAME`` attr module name of registerer 322 ``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier 323 (EUI-64), as defined by the 324 IEEE 1588 standard 325 ``DPLL_A_TYPE`` attr type of dpll device 326 ==================================== ================================= 327 328 ==================================== ================================= 329 ``DPLL_CMD_DEVICE_GET`` command to get device info or 330 dump list of available devices 331 ``DPLL_A_ID`` attr unique dpll device ID 332 ``DPLL_A_MODULE_NAME`` attr module name of registerer 333 ``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier 334 (EUI-64), as defined by the 335 IEEE 1588 standard 336 ``DPLL_A_MODE`` attr selection mode 337 ``DPLL_A_MODE_SUPPORTED`` attr available selection modes 338 ``DPLL_A_LOCK_STATUS`` attr dpll device lock status 339 ``DPLL_A_TEMP`` attr device temperature info 340 ``DPLL_A_TYPE`` attr type of dpll device 341 ==================================== ================================= 342 343 ==================================== ================================= 344 ``DPLL_CMD_DEVICE_SET`` command to set dpll device config 345 ``DPLL_A_ID`` attr internal dpll device index 346 ``DPLL_A_MODE`` attr selection mode to configure 347 ==================================== ================================= 348 349Constants identifying command types for pins uses a 350``DPLL_CMD_PIN_`` prefix and suffix according to command purpose. 351The pin related attributes use a ``DPLL_A_PIN_`` prefix and suffix 352according to attribute purpose. 353 354 ==================================== ================================= 355 ``DPLL_CMD_PIN_ID_GET`` command to get pin ID 356 ``DPLL_A_PIN_MODULE_NAME`` attr module name of registerer 357 ``DPLL_A_PIN_CLOCK_ID`` attr Unique Clock Identifier 358 (EUI-64), as defined by the 359 IEEE 1588 standard 360 ``DPLL_A_PIN_BOARD_LABEL`` attr pin board label provided 361 by registerer 362 ``DPLL_A_PIN_PANEL_LABEL`` attr pin panel label provided 363 by registerer 364 ``DPLL_A_PIN_PACKAGE_LABEL`` attr pin package label provided 365 by registerer 366 ``DPLL_A_PIN_TYPE`` attr type of a pin 367 ==================================== ================================= 368 369 ==================================== ================================== 370 ``DPLL_CMD_PIN_GET`` command to get pin info or dump 371 list of available pins 372 ``DPLL_A_PIN_ID`` attr unique a pin ID 373 ``DPLL_A_PIN_MODULE_NAME`` attr module name of registerer 374 ``DPLL_A_PIN_CLOCK_ID`` attr Unique Clock Identifier 375 (EUI-64), as defined by the 376 IEEE 1588 standard 377 ``DPLL_A_PIN_BOARD_LABEL`` attr pin board label provided 378 by registerer 379 ``DPLL_A_PIN_PANEL_LABEL`` attr pin panel label provided 380 by registerer 381 ``DPLL_A_PIN_PACKAGE_LABEL`` attr pin package label provided 382 by registerer 383 ``DPLL_A_PIN_TYPE`` attr type of a pin 384 ``DPLL_A_PIN_FREQUENCY`` attr current frequency of a pin 385 ``DPLL_A_PIN_FREQUENCY_SUPPORTED`` nested attr provides supported 386 frequencies 387 ``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency 388 ``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency 389 ``DPLL_A_PIN_PHASE_ADJUST_GRAN`` attr granularity of phase 390 adjustment value 391 ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase 392 adjustment 393 ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase 394 adjustment 395 ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase 396 adjustment on parent device 397 ``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent device 398 the pin is connected with 399 ``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id 400 ``DPLL_A_PIN_PRIO`` attr priority of pin on the 401 dpll device 402 ``DPLL_A_PIN_STATE`` attr state of pin on the parent 403 dpll device 404 ``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the 405 parent dpll device 406 ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference 407 between a pin and parent dpll 408 ``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin 409 the pin is connected with 410 ``DPLL_A_PIN_PARENT_ID`` attr parent pin id 411 ``DPLL_A_PIN_STATE`` attr state of pin on the parent 412 pin 413 ``DPLL_A_PIN_CAPABILITIES`` attr bitmask of pin capabilities 414 ==================================== ================================== 415 416 ==================================== ================================= 417 ``DPLL_CMD_PIN_SET`` command to set pins configuration 418 ``DPLL_A_PIN_ID`` attr unique a pin ID 419 ``DPLL_A_PIN_FREQUENCY`` attr requested frequency of a pin 420 ``DPLL_A_PIN_PHASE_ADJUST`` attr requested value of phase 421 adjustment on parent device 422 ``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent dpll 423 device configuration request 424 ``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id 425 ``DPLL_A_PIN_DIRECTION`` attr requested direction of a pin 426 ``DPLL_A_PIN_PRIO`` attr requested priority of pin on 427 the dpll device 428 ``DPLL_A_PIN_STATE`` attr requested state of pin on 429 the dpll device 430 ``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin 431 configuration request 432 ``DPLL_A_PIN_PARENT_ID`` attr parent pin id 433 ``DPLL_A_PIN_STATE`` attr requested state of pin on 434 parent pin 435 ==================================== ================================= 436 437Netlink dump requests 438===================== 439 440The ``DPLL_CMD_DEVICE_GET`` and ``DPLL_CMD_PIN_GET`` commands are 441capable of dump type netlink requests, in which case the response is in 442the same format as for their ``do`` request, but every device or pin 443registered in the system is returned. 444 445SET commands format 446=================== 447 448``DPLL_CMD_DEVICE_SET`` - to target a dpll device, the user provides 449``DPLL_A_ID``, which is unique identifier of dpll device in the system, 450as well as parameter being configured (``DPLL_A_MODE``). 451 452``DPLL_CMD_PIN_SET`` - to target a pin user must provide a 453``DPLL_A_PIN_ID``, which is unique identifier of a pin in the system. 454Also configured pin parameters must be added. 455If ``DPLL_A_PIN_FREQUENCY`` is configured, this affects all the dpll 456devices that are connected with the pin, that is why frequency attribute 457shall not be enclosed in ``DPLL_A_PIN_PARENT_DEVICE``. 458Other attributes: ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE`` or 459``DPLL_A_PIN_DIRECTION`` must be enclosed in 460``DPLL_A_PIN_PARENT_DEVICE`` as their configuration relates to only one 461of parent dplls, targeted by ``DPLL_A_PIN_PARENT_ID`` attribute which is 462also required inside that nest. 463For MUX-type pins the ``DPLL_A_PIN_STATE`` attribute is configured in 464similar way, by enclosing required state in ``DPLL_A_PIN_PARENT_PIN`` 465nested attribute and targeted parent pin id in ``DPLL_A_PIN_PARENT_ID``. 466 467In general, it is possible to configure multiple parameters at once, but 468internally each parameter change will be invoked separately, where order 469of configuration is not guaranteed by any means. 470 471Configuration pre-defined enums 472=============================== 473 474.. kernel-doc:: include/uapi/linux/dpll.h 475 476Notifications 477============= 478 479dpll device can provide notifications regarding status changes of the 480device, i.e. lock status changes, input/output changes or other alarms. 481There is one multicast group that is used to notify user-space apps via 482netlink socket: ``DPLL_MCGRP_MONITOR`` 483 484Notifications messages: 485 486 ============================== ===================================== 487 ``DPLL_CMD_DEVICE_CREATE_NTF`` dpll device was created 488 ``DPLL_CMD_DEVICE_DELETE_NTF`` dpll device was deleted 489 ``DPLL_CMD_DEVICE_CHANGE_NTF`` dpll device has changed 490 ``DPLL_CMD_PIN_CREATE_NTF`` dpll pin was created 491 ``DPLL_CMD_PIN_DELETE_NTF`` dpll pin was deleted 492 ``DPLL_CMD_PIN_CHANGE_NTF`` dpll pin has changed 493 ============================== ===================================== 494 495Events format is the same as for the corresponding get command. 496Format of ``DPLL_CMD_DEVICE_`` events is the same as response of 497``DPLL_CMD_DEVICE_GET``. 498Format of ``DPLL_CMD_PIN_`` events is same as response of 499``DPLL_CMD_PIN_GET``. 500 501Device driver implementation 502============================ 503 504Device is allocated by dpll_device_get() call. Second call with the 505same arguments will not create new object but provides pointer to 506previously created device for given arguments, it also increases 507refcount of that object. 508Device is deallocated by dpll_device_put() call, which first 509decreases the refcount, once refcount is cleared the object is 510destroyed. 511 512Device should implement set of operations and register device via 513dpll_device_register() at which point it becomes available to the 514users. Multiple driver instances can obtain reference to it with 515dpll_device_get(), as well as register dpll device with their own 516ops and priv. 517 518The pins are allocated separately with dpll_pin_get(), it works 519similarly to dpll_device_get(). Function first creates object and then 520for each call with the same arguments only the object refcount 521increases. Also dpll_pin_put() works similarly to dpll_device_put(). 522 523A pin can be registered with parent dpll device or parent pin, depending 524on hardware needs. Each registration requires registerer to provide set 525of pin callbacks, and private data pointer for calling them: 526 527- dpll_pin_register() - register pin with a dpll device, 528- dpll_pin_on_pin_register() - register pin with another MUX type pin. 529 530Notifications of adding or removing dpll devices are created within 531subsystem itself. 532Notifications about registering/deregistering pins are also invoked by 533the subsystem. 534Notifications about status changes either of dpll device or a pin are 535invoked in two ways: 536 537- after successful change was requested on dpll subsystem, the subsystem 538 calls corresponding notification, 539- requested by device driver with dpll_device_change_ntf() or 540 dpll_pin_change_ntf() when driver informs about the status change. 541 542The device driver using dpll interface is not required to implement all 543the callback operation. Nevertheless, there are few required to be 544implemented. 545Required dpll device level callback operations: 546 547- ``.mode_get``, 548- ``.lock_status_get``. 549 550Required pin level callback operations: 551 552- ``.state_on_dpll_get`` (pins registered with dpll device), 553- ``.state_on_pin_get`` (pins registered with parent pin), 554- ``.direction_get``. 555 556Every other operation handler is checked for existence and 557``-EOPNOTSUPP`` is returned in case of absence of specific handler. 558 559The simplest implementation is in the OCP TimeCard driver. The ops 560structures are defined like this: 561 562.. code-block:: c 563 564 static const struct dpll_device_ops dpll_ops = { 565 .lock_status_get = ptp_ocp_dpll_lock_status_get, 566 .mode_get = ptp_ocp_dpll_mode_get, 567 .mode_supported = ptp_ocp_dpll_mode_supported, 568 }; 569 570 static const struct dpll_pin_ops dpll_pins_ops = { 571 .frequency_get = ptp_ocp_dpll_frequency_get, 572 .frequency_set = ptp_ocp_dpll_frequency_set, 573 .direction_get = ptp_ocp_dpll_direction_get, 574 .direction_set = ptp_ocp_dpll_direction_set, 575 .state_on_dpll_get = ptp_ocp_dpll_state_get, 576 }; 577 578The registration part is then looks like this part: 579 580.. code-block:: c 581 582 clkid = pci_get_dsn(pdev); 583 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE); 584 if (IS_ERR(bp->dpll)) { 585 err = PTR_ERR(bp->dpll); 586 dev_err(&pdev->dev, "dpll_device_alloc failed\n"); 587 goto out; 588 } 589 590 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp); 591 if (err) 592 goto out; 593 594 for (i = 0; i < OCP_SMA_NUM; i++) { 595 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop); 596 if (IS_ERR(bp->sma[i].dpll_pin)) { 597 err = PTR_ERR(bp->dpll); 598 goto out_dpll; 599 } 600 601 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, 602 &bp->sma[i]); 603 if (err) { 604 dpll_pin_put(bp->sma[i].dpll_pin); 605 goto out_dpll; 606 } 607 } 608 609In the error path we have to rewind every allocation in the reverse order: 610 611.. code-block:: c 612 613 while (i) { 614 --i; 615 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); 616 dpll_pin_put(bp->sma[i].dpll_pin); 617 } 618 dpll_device_put(bp->dpll); 619 620More complex example can be found in Intel's ICE driver or nVidia's mlx5 driver. 621 622SyncE enablement 623================ 624For SyncE enablement it is required to allow control over dpll device 625for a software application which monitors and configures the inputs of 626dpll device in response to current state of a dpll device and its 627inputs. 628In such scenario, dpll device input signal shall be also configurable 629to drive dpll with signal recovered from the PHY netdevice. 630This is done by exposing a pin to the netdevice - attaching pin to the 631netdevice itself with 632``dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin)``. 633Exposed pin id handle ``DPLL_A_PIN_ID`` is then identifiable by the user 634as it is attached to rtnetlink respond to get ``RTM_NEWLINK`` command in 635nested attribute ``IFLA_DPLL_PIN``. 636