1.. SPDX-License-Identifier: GPL-2.0 2 3=============================== 4The Linux kernel dpll subsystem 5=============================== 6 7DPLL 8==== 9 10PLL - Phase Locked Loop is an electronic circuit which syntonizes clock 11signal of a device with an external clock signal. Effectively enabling 12device to run on the same clock signal beat as provided on a PLL input. 13 14DPLL - Digital Phase Locked Loop is an integrated circuit which in 15addition to plain PLL behavior incorporates a digital phase detector 16and may have digital divider in the loop. As a result, the frequency on 17DPLL's input and output may be configurable. 18 19Subsystem 20========= 21 22The main purpose of dpll subsystem is to provide general interface 23to configure devices that use any kind of Digital PLL and could use 24different sources of input signal to synchronize to, as well as 25different types of outputs. 26The main interface is NETLINK_GENERIC based protocol with an event 27monitoring multicast group defined. 28 29Device object 30============= 31 32Single dpll device object means single Digital PLL circuit and bunch of 33connected pins. 34It reports the supported modes of operation and current status to the 35user in response to the `do` request of netlink command 36``DPLL_CMD_DEVICE_GET`` and list of dplls registered in the subsystem 37with `dump` netlink request of the same command. 38Changing the configuration of dpll device is done with `do` request of 39netlink ``DPLL_CMD_DEVICE_SET`` command. 40A device handle is ``DPLL_A_ID``, it shall be provided to get or set 41configuration of particular device in the system. It can be obtained 42with a ``DPLL_CMD_DEVICE_GET`` `dump` request or 43a ``DPLL_CMD_DEVICE_ID_GET`` `do` request, where the one must provide 44attributes that result in single device match. 45 46Pin object 47========== 48 49A pin is amorphic object which represents either input or output, it 50could be internal component of the device, as well as externally 51connected. 52The number of pins per dpll vary, but usually multiple pins shall be 53provided for a single dpll device. 54Pin's properties, capabilities and status is provided to the user in 55response to `do` request of netlink ``DPLL_CMD_PIN_GET`` command. 56It is also possible to list all the pins that were registered in the 57system with `dump` request of ``DPLL_CMD_PIN_GET`` command. 58Configuration of a pin can be changed by `do` request of netlink 59``DPLL_CMD_PIN_SET`` command. 60Pin handle is a ``DPLL_A_PIN_ID``, it shall be provided to get or set 61configuration of particular pin in the system. It can be obtained with 62``DPLL_CMD_PIN_GET`` `dump` request or ``DPLL_CMD_PIN_ID_GET`` `do` 63request, where user provides attributes that result in single pin match. 64 65Pin selection 66============= 67 68In general, selected pin (the one which signal is driving the dpll 69device) can be obtained from ``DPLL_A_PIN_STATE`` attribute, and only 70one pin shall be in ``DPLL_PIN_STATE_CONNECTED`` state for any dpll 71device. 72 73Pin selection can be done either manually or automatically, depending 74on hardware capabilities and active dpll device work mode 75(``DPLL_A_MODE`` attribute). The consequence is that there are 76differences for each mode in terms of available pin states, as well as 77for the states the user can request for a dpll device. 78 79In manual mode (``DPLL_MODE_MANUAL``) the user can request or receive 80one of following pin states: 81 82- ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device 83- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll 84 device 85 86In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can request or 87receive one of following pin states: 88 89- ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid 90 input for automatic selection algorithm 91- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as 92 a valid input for automatic selection algorithm 93 94In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can only receive 95pin state ``DPLL_PIN_STATE_CONNECTED`` once automatic selection 96algorithm locks a dpll device with one of the inputs. 97 98Shared pins 99=========== 100 101A single pin object can be attached to multiple dpll devices. 102Then there are two groups of configuration knobs: 103 1041) Set on a pin - the configuration affects all dpll devices pin is 105 registered to (i.e., ``DPLL_A_PIN_FREQUENCY``), 1062) Set on a pin-dpll tuple - the configuration affects only selected 107 dpll device (i.e., ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE``, 108 ``DPLL_A_PIN_DIRECTION``). 109 110MUX-type pins 111============= 112 113A pin can be MUX-type, it aggregates child pins and serves as a pin 114multiplexer. One or more pins are registered with MUX-type instead of 115being directly registered to a dpll device. 116Pins registered with a MUX-type pin provide user with additional nested 117attribute ``DPLL_A_PIN_PARENT_PIN`` for each parent they were registered 118with. 119If a pin was registered with multiple parent pins, they behave like a 120multiple output multiplexer. In this case output of a 121``DPLL_CMD_PIN_GET`` would contain multiple pin-parent nested 122attributes with current state related to each parent, like:: 123 124 'pin': [{{ 125 'clock-id': 282574471561216, 126 'module-name': 'ice', 127 'capabilities': 4, 128 'id': 13, 129 'parent-pin': [ 130 {'parent-id': 2, 'state': 'connected'}, 131 {'parent-id': 3, 'state': 'disconnected'} 132 ], 133 'type': 'synce-eth-port' 134 }}] 135 136Only one child pin can provide its signal to the parent MUX-type pin at 137a time, the selection is done by requesting change of a child pin state 138on desired parent, with the use of ``DPLL_A_PIN_PARENT`` nested 139attribute. Example of netlink `set state on parent pin` message format: 140 141 ========================== ============================================= 142 ``DPLL_A_PIN_ID`` child pin id 143 ``DPLL_A_PIN_PARENT_PIN`` nested attribute for requesting configuration 144 related to parent pin 145 ``DPLL_A_PIN_PARENT_ID`` parent pin id 146 ``DPLL_A_PIN_STATE`` requested pin state on parent 147 ========================== ============================================= 148 149Pin priority 150============ 151 152Some devices might offer a capability of automatic pin selection mode 153(enum value ``DPLL_MODE_AUTOMATIC`` of ``DPLL_A_MODE`` attribute). 154Usually, automatic selection is performed on the hardware level, which 155means only pins directly connected to the dpll can be used for automatic 156input pin selection. 157In automatic selection mode, the user cannot manually select a input 158pin for the device, instead the user shall provide all directly 159connected pins with a priority ``DPLL_A_PIN_PRIO``, the device would 160pick a highest priority valid signal and use it to control the DPLL 161device. Example of netlink `set priority on parent pin` message format: 162 163 ============================ ============================================= 164 ``DPLL_A_PIN_ID`` configured pin id 165 ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting configuration 166 related to parent dpll device 167 ``DPLL_A_PIN_PARENT_ID`` parent dpll device id 168 ``DPLL_A_PIN_PRIO`` requested pin prio on parent dpll 169 ============================ ============================================= 170 171Child pin of MUX-type pin is not capable of automatic input pin selection, 172in order to configure active input of a MUX-type pin, the user needs to 173request desired pin state of the child pin on the parent pin, 174as described in the ``MUX-type pins`` chapter. 175 176Phase offset measurement and adjustment 177======================================== 178 179Device may provide ability to measure a phase difference between signals 180on a pin and its parent dpll device. If pin-dpll phase offset measurement 181is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET`` 182attribute for each parent dpll device. The reported phase offset may be 183computed as the average of prior values and the current measurement, using 184the following formula: 185 186.. math:: 187 curr\_avg = prev\_avg * \frac{2^N-1}{2^N} + new\_val * \frac{1}{2^N} 188 189where `curr_avg` is the current reported phase offset, `prev_avg` is the 190previously reported value, `new_val` is the current measurement, and `N` is 191the averaging factor. Configured averaging factor value is provided with 192``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attribute of a device and value change can 193be requested with the same attribute with ``DPLL_CMD_DEVICE_SET`` command. 194 195 ================================== ====================================== 196 ``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attr configured value of phase offset 197 averaging factor 198 ================================== ====================================== 199 200Device may also provide ability to adjust a signal phase on a pin. 201If pin phase adjustment is supported, minimal and maximal values that pin 202handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond 203with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX`` 204attributes. Configured phase adjust value is provided with 205``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be 206requested with the same attribute with ``DPLL_CMD_PIN_SET`` command. 207 208 =============================== ====================================== 209 ``DPLL_A_PIN_ID`` configured pin id 210 ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment 211 ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment 212 ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase 213 adjustment on parent dpll device 214 ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting 215 configuration on given parent dpll 216 device 217 ``DPLL_A_PIN_PARENT_ID`` parent dpll device id 218 ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference 219 between a pin and parent dpll device 220 =============================== ====================================== 221 222All phase related values are provided in pico seconds, which represents 223time difference between signals phase. The negative value means that 224phase of signal on pin is earlier in time than dpll's signal. Positive 225value means that phase of signal on pin is later in time than signal of 226a dpll. 227 228Phase adjust (also min and max) values are integers, but measured phase 229offset values are fractional with 3-digit decimal places and shell be 230divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and 231modulo divided to get fractional part. 232 233Phase offset monitor 234==================== 235 236Phase offset measurement is typically performed against the current active 237source. However, some DPLL (Digital Phase-Locked Loop) devices may offer 238the capability to monitor phase offsets across all available inputs. 239The attribute and current feature state shall be included in the response 240message of the ``DPLL_CMD_DEVICE_GET`` command for supported DPLL devices. 241In such cases, users can also control the feature using the 242``DPLL_CMD_DEVICE_SET`` command by setting the ``enum dpll_feature_state`` 243values for the attribute. 244Once enabled the phase offset measurements for the input shall be returned 245in the ``DPLL_A_PIN_PHASE_OFFSET`` attribute. 246 247 =============================== ======================== 248 ``DPLL_A_PHASE_OFFSET_MONITOR`` attr state of a feature 249 =============================== ======================== 250 251Embedded SYNC 252============= 253 254Device may provide ability to use Embedded SYNC feature. It allows 255to embed additional SYNC signal into the base frequency of a pin - a one 256special pulse of base frequency signal every time SYNC signal pulse 257happens. The user can configure the frequency of Embedded SYNC. 258The Embedded SYNC capability is always related to a given base frequency 259and HW capabilities. The user is provided a range of Embedded SYNC 260frequencies supported, depending on current base frequency configured for 261the pin. 262 263 ========================================= ================================= 264 ``DPLL_A_PIN_ESYNC_FREQUENCY`` current Embedded SYNC frequency 265 ``DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED`` nest available Embedded SYNC 266 frequency ranges 267 ``DPLL_A_PIN_FREQUENCY_MIN`` attr minimum value of frequency 268 ``DPLL_A_PIN_FREQUENCY_MAX`` attr maximum value of frequency 269 ``DPLL_A_PIN_ESYNC_PULSE`` pulse type of Embedded SYNC 270 ========================================= ================================= 271 272Reference SYNC 273============== 274 275The device may support the Reference SYNC feature, which allows the combination 276of two inputs into a input pair. In this configuration, clock signals 277from both inputs are used to synchronize the DPLL device. The higher frequency 278signal is utilized for the loop bandwidth of the DPLL, while the lower frequency 279signal is used to syntonize the output signal of the DPLL device. This feature 280enables the provision of a high-quality loop bandwidth signal from an external 281source. 282 283A capable input provides a list of inputs that can be bound with to create 284Reference SYNC. To control this feature, the user must request a desired 285state for a target pin: use ``DPLL_PIN_STATE_CONNECTED`` to enable or 286``DPLL_PIN_STATE_DISCONNECTED`` to disable the feature. An input pin can be 287bound to only one other pin at any given time. 288 289 ============================== ========================================== 290 ``DPLL_A_PIN_REFERENCE_SYNC`` nested attribute for providing info or 291 requesting configuration of the Reference 292 SYNC feature 293 ``DPLL_A_PIN_ID`` target pin id for Reference SYNC feature 294 ``DPLL_A_PIN_STATE`` state of Reference SYNC connection 295 ============================== ========================================== 296 297Configuration commands group 298============================ 299 300Configuration commands are used to get information about registered 301dpll devices (and pins), as well as set configuration of device or pins. 302As dpll devices must be abstracted and reflect real hardware, 303there is no way to add new dpll device via netlink from user space and 304each device should be registered by its driver. 305 306All netlink commands require ``GENL_ADMIN_PERM``. This is to prevent 307any spamming/DoS from unauthorized userspace applications. 308 309List of netlink commands with possible attributes 310================================================= 311 312Constants identifying command types for dpll device uses a 313``DPLL_CMD_`` prefix and suffix according to command purpose. 314The dpll device related attributes use a ``DPLL_A_`` prefix and 315suffix according to attribute purpose. 316 317 ==================================== ================================= 318 ``DPLL_CMD_DEVICE_ID_GET`` command to get device ID 319 ``DPLL_A_MODULE_NAME`` attr module name of registerer 320 ``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier 321 (EUI-64), as defined by the 322 IEEE 1588 standard 323 ``DPLL_A_TYPE`` attr type of dpll device 324 ==================================== ================================= 325 326 ==================================== ================================= 327 ``DPLL_CMD_DEVICE_GET`` command to get device info or 328 dump list of available devices 329 ``DPLL_A_ID`` attr unique dpll device ID 330 ``DPLL_A_MODULE_NAME`` attr module name of registerer 331 ``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier 332 (EUI-64), as defined by the 333 IEEE 1588 standard 334 ``DPLL_A_MODE`` attr selection mode 335 ``DPLL_A_MODE_SUPPORTED`` attr available selection modes 336 ``DPLL_A_LOCK_STATUS`` attr dpll device lock status 337 ``DPLL_A_TEMP`` attr device temperature info 338 ``DPLL_A_TYPE`` attr type of dpll device 339 ==================================== ================================= 340 341 ==================================== ================================= 342 ``DPLL_CMD_DEVICE_SET`` command to set dpll device config 343 ``DPLL_A_ID`` attr internal dpll device index 344 ``DPLL_A_MODE`` attr selection mode to configure 345 ==================================== ================================= 346 347Constants identifying command types for pins uses a 348``DPLL_CMD_PIN_`` prefix and suffix according to command purpose. 349The pin related attributes use a ``DPLL_A_PIN_`` prefix and suffix 350according to attribute purpose. 351 352 ==================================== ================================= 353 ``DPLL_CMD_PIN_ID_GET`` command to get pin ID 354 ``DPLL_A_PIN_MODULE_NAME`` attr module name of registerer 355 ``DPLL_A_PIN_CLOCK_ID`` attr Unique Clock Identifier 356 (EUI-64), as defined by the 357 IEEE 1588 standard 358 ``DPLL_A_PIN_BOARD_LABEL`` attr pin board label provided 359 by registerer 360 ``DPLL_A_PIN_PANEL_LABEL`` attr pin panel label provided 361 by registerer 362 ``DPLL_A_PIN_PACKAGE_LABEL`` attr pin package label provided 363 by registerer 364 ``DPLL_A_PIN_TYPE`` attr type of a pin 365 ==================================== ================================= 366 367 ==================================== ================================== 368 ``DPLL_CMD_PIN_GET`` command to get pin info or dump 369 list of available pins 370 ``DPLL_A_PIN_ID`` attr unique a pin ID 371 ``DPLL_A_PIN_MODULE_NAME`` attr module name of registerer 372 ``DPLL_A_PIN_CLOCK_ID`` attr Unique Clock Identifier 373 (EUI-64), as defined by the 374 IEEE 1588 standard 375 ``DPLL_A_PIN_BOARD_LABEL`` attr pin board label provided 376 by registerer 377 ``DPLL_A_PIN_PANEL_LABEL`` attr pin panel label provided 378 by registerer 379 ``DPLL_A_PIN_PACKAGE_LABEL`` attr pin package label provided 380 by registerer 381 ``DPLL_A_PIN_TYPE`` attr type of a pin 382 ``DPLL_A_PIN_FREQUENCY`` attr current frequency of a pin 383 ``DPLL_A_PIN_FREQUENCY_SUPPORTED`` nested attr provides supported 384 frequencies 385 ``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency 386 ``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency 387 ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase 388 adjustment 389 ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase 390 adjustment 391 ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase 392 adjustment on parent device 393 ``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent device 394 the pin is connected with 395 ``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id 396 ``DPLL_A_PIN_PRIO`` attr priority of pin on the 397 dpll device 398 ``DPLL_A_PIN_STATE`` attr state of pin on the parent 399 dpll device 400 ``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the 401 parent dpll device 402 ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference 403 between a pin and parent dpll 404 ``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin 405 the pin is connected with 406 ``DPLL_A_PIN_PARENT_ID`` attr parent pin id 407 ``DPLL_A_PIN_STATE`` attr state of pin on the parent 408 pin 409 ``DPLL_A_PIN_CAPABILITIES`` attr bitmask of pin capabilities 410 ==================================== ================================== 411 412 ==================================== ================================= 413 ``DPLL_CMD_PIN_SET`` command to set pins configuration 414 ``DPLL_A_PIN_ID`` attr unique a pin ID 415 ``DPLL_A_PIN_FREQUENCY`` attr requested frequency of a pin 416 ``DPLL_A_PIN_PHASE_ADJUST`` attr requested value of phase 417 adjustment on parent device 418 ``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent dpll 419 device configuration request 420 ``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id 421 ``DPLL_A_PIN_DIRECTION`` attr requested direction of a pin 422 ``DPLL_A_PIN_PRIO`` attr requested priority of pin on 423 the dpll device 424 ``DPLL_A_PIN_STATE`` attr requested state of pin on 425 the dpll device 426 ``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin 427 configuration request 428 ``DPLL_A_PIN_PARENT_ID`` attr parent pin id 429 ``DPLL_A_PIN_STATE`` attr requested state of pin on 430 parent pin 431 ==================================== ================================= 432 433Netlink dump requests 434===================== 435 436The ``DPLL_CMD_DEVICE_GET`` and ``DPLL_CMD_PIN_GET`` commands are 437capable of dump type netlink requests, in which case the response is in 438the same format as for their ``do`` request, but every device or pin 439registered in the system is returned. 440 441SET commands format 442=================== 443 444``DPLL_CMD_DEVICE_SET`` - to target a dpll device, the user provides 445``DPLL_A_ID``, which is unique identifier of dpll device in the system, 446as well as parameter being configured (``DPLL_A_MODE``). 447 448``DPLL_CMD_PIN_SET`` - to target a pin user must provide a 449``DPLL_A_PIN_ID``, which is unique identifier of a pin in the system. 450Also configured pin parameters must be added. 451If ``DPLL_A_PIN_FREQUENCY`` is configured, this affects all the dpll 452devices that are connected with the pin, that is why frequency attribute 453shall not be enclosed in ``DPLL_A_PIN_PARENT_DEVICE``. 454Other attributes: ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE`` or 455``DPLL_A_PIN_DIRECTION`` must be enclosed in 456``DPLL_A_PIN_PARENT_DEVICE`` as their configuration relates to only one 457of parent dplls, targeted by ``DPLL_A_PIN_PARENT_ID`` attribute which is 458also required inside that nest. 459For MUX-type pins the ``DPLL_A_PIN_STATE`` attribute is configured in 460similar way, by enclosing required state in ``DPLL_A_PIN_PARENT_PIN`` 461nested attribute and targeted parent pin id in ``DPLL_A_PIN_PARENT_ID``. 462 463In general, it is possible to configure multiple parameters at once, but 464internally each parameter change will be invoked separately, where order 465of configuration is not guaranteed by any means. 466 467Configuration pre-defined enums 468=============================== 469 470.. kernel-doc:: include/uapi/linux/dpll.h 471 472Notifications 473============= 474 475dpll device can provide notifications regarding status changes of the 476device, i.e. lock status changes, input/output changes or other alarms. 477There is one multicast group that is used to notify user-space apps via 478netlink socket: ``DPLL_MCGRP_MONITOR`` 479 480Notifications messages: 481 482 ============================== ===================================== 483 ``DPLL_CMD_DEVICE_CREATE_NTF`` dpll device was created 484 ``DPLL_CMD_DEVICE_DELETE_NTF`` dpll device was deleted 485 ``DPLL_CMD_DEVICE_CHANGE_NTF`` dpll device has changed 486 ``DPLL_CMD_PIN_CREATE_NTF`` dpll pin was created 487 ``DPLL_CMD_PIN_DELETE_NTF`` dpll pin was deleted 488 ``DPLL_CMD_PIN_CHANGE_NTF`` dpll pin has changed 489 ============================== ===================================== 490 491Events format is the same as for the corresponding get command. 492Format of ``DPLL_CMD_DEVICE_`` events is the same as response of 493``DPLL_CMD_DEVICE_GET``. 494Format of ``DPLL_CMD_PIN_`` events is same as response of 495``DPLL_CMD_PIN_GET``. 496 497Device driver implementation 498============================ 499 500Device is allocated by dpll_device_get() call. Second call with the 501same arguments will not create new object but provides pointer to 502previously created device for given arguments, it also increases 503refcount of that object. 504Device is deallocated by dpll_device_put() call, which first 505decreases the refcount, once refcount is cleared the object is 506destroyed. 507 508Device should implement set of operations and register device via 509dpll_device_register() at which point it becomes available to the 510users. Multiple driver instances can obtain reference to it with 511dpll_device_get(), as well as register dpll device with their own 512ops and priv. 513 514The pins are allocated separately with dpll_pin_get(), it works 515similarly to dpll_device_get(). Function first creates object and then 516for each call with the same arguments only the object refcount 517increases. Also dpll_pin_put() works similarly to dpll_device_put(). 518 519A pin can be registered with parent dpll device or parent pin, depending 520on hardware needs. Each registration requires registerer to provide set 521of pin callbacks, and private data pointer for calling them: 522 523- dpll_pin_register() - register pin with a dpll device, 524- dpll_pin_on_pin_register() - register pin with another MUX type pin. 525 526Notifications of adding or removing dpll devices are created within 527subsystem itself. 528Notifications about registering/deregistering pins are also invoked by 529the subsystem. 530Notifications about status changes either of dpll device or a pin are 531invoked in two ways: 532 533- after successful change was requested on dpll subsystem, the subsystem 534 calls corresponding notification, 535- requested by device driver with dpll_device_change_ntf() or 536 dpll_pin_change_ntf() when driver informs about the status change. 537 538The device driver using dpll interface is not required to implement all 539the callback operation. Nevertheless, there are few required to be 540implemented. 541Required dpll device level callback operations: 542 543- ``.mode_get``, 544- ``.lock_status_get``. 545 546Required pin level callback operations: 547 548- ``.state_on_dpll_get`` (pins registered with dpll device), 549- ``.state_on_pin_get`` (pins registered with parent pin), 550- ``.direction_get``. 551 552Every other operation handler is checked for existence and 553``-EOPNOTSUPP`` is returned in case of absence of specific handler. 554 555The simplest implementation is in the OCP TimeCard driver. The ops 556structures are defined like this: 557 558.. code-block:: c 559 560 static const struct dpll_device_ops dpll_ops = { 561 .lock_status_get = ptp_ocp_dpll_lock_status_get, 562 .mode_get = ptp_ocp_dpll_mode_get, 563 .mode_supported = ptp_ocp_dpll_mode_supported, 564 }; 565 566 static const struct dpll_pin_ops dpll_pins_ops = { 567 .frequency_get = ptp_ocp_dpll_frequency_get, 568 .frequency_set = ptp_ocp_dpll_frequency_set, 569 .direction_get = ptp_ocp_dpll_direction_get, 570 .direction_set = ptp_ocp_dpll_direction_set, 571 .state_on_dpll_get = ptp_ocp_dpll_state_get, 572 }; 573 574The registration part is then looks like this part: 575 576.. code-block:: c 577 578 clkid = pci_get_dsn(pdev); 579 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE); 580 if (IS_ERR(bp->dpll)) { 581 err = PTR_ERR(bp->dpll); 582 dev_err(&pdev->dev, "dpll_device_alloc failed\n"); 583 goto out; 584 } 585 586 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp); 587 if (err) 588 goto out; 589 590 for (i = 0; i < OCP_SMA_NUM; i++) { 591 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop); 592 if (IS_ERR(bp->sma[i].dpll_pin)) { 593 err = PTR_ERR(bp->dpll); 594 goto out_dpll; 595 } 596 597 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, 598 &bp->sma[i]); 599 if (err) { 600 dpll_pin_put(bp->sma[i].dpll_pin); 601 goto out_dpll; 602 } 603 } 604 605In the error path we have to rewind every allocation in the reverse order: 606 607.. code-block:: c 608 609 while (i) { 610 --i; 611 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); 612 dpll_pin_put(bp->sma[i].dpll_pin); 613 } 614 dpll_device_put(bp->dpll); 615 616More complex example can be found in Intel's ICE driver or nVidia's mlx5 driver. 617 618SyncE enablement 619================ 620For SyncE enablement it is required to allow control over dpll device 621for a software application which monitors and configures the inputs of 622dpll device in response to current state of a dpll device and its 623inputs. 624In such scenario, dpll device input signal shall be also configurable 625to drive dpll with signal recovered from the PHY netdevice. 626This is done by exposing a pin to the netdevice - attaching pin to the 627netdevice itself with 628``dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin)``. 629Exposed pin id handle ``DPLL_A_PIN_ID`` is then identifiable by the user 630as it is attached to rtnetlink respond to get ``RTM_NEWLINK`` command in 631nested attribute ``IFLA_DPLL_PIN``. 632