1.. SPDX-License-Identifier: GPL-2.0 2 3=============================== 4The Linux kernel dpll subsystem 5=============================== 6 7DPLL 8==== 9 10PLL - Phase Locked Loop is an electronic circuit which syntonizes clock 11signal of a device with an external clock signal. Effectively enabling 12device to run on the same clock signal beat as provided on a PLL input. 13 14DPLL - Digital Phase Locked Loop is an integrated circuit which in 15addition to plain PLL behavior incorporates a digital phase detector 16and may have digital divider in the loop. As a result, the frequency on 17DPLL's input and output may be configurable. 18 19Subsystem 20========= 21 22The main purpose of dpll subsystem is to provide general interface 23to configure devices that use any kind of Digital PLL and could use 24different sources of input signal to synchronize to, as well as 25different types of outputs. 26The main interface is NETLINK_GENERIC based protocol with an event 27monitoring multicast group defined. 28 29Device object 30============= 31 32Single dpll device object means single Digital PLL circuit and bunch of 33connected pins. 34It reports the supported modes of operation and current status to the 35user in response to the `do` request of netlink command 36``DPLL_CMD_DEVICE_GET`` and list of dplls registered in the subsystem 37with `dump` netlink request of the same command. 38Changing the configuration of dpll device is done with `do` request of 39netlink ``DPLL_CMD_DEVICE_SET`` command. 40A device handle is ``DPLL_A_ID``, it shall be provided to get or set 41configuration of particular device in the system. It can be obtained 42with a ``DPLL_CMD_DEVICE_GET`` `dump` request or 43a ``DPLL_CMD_DEVICE_ID_GET`` `do` request, where the one must provide 44attributes that result in single device match. 45 46Pin object 47========== 48 49A pin is amorphic object which represents either input or output, it 50could be internal component of the device, as well as externally 51connected. 52The number of pins per dpll vary, but usually multiple pins shall be 53provided for a single dpll device. 54Pin's properties, capabilities and status is provided to the user in 55response to `do` request of netlink ``DPLL_CMD_PIN_GET`` command. 56It is also possible to list all the pins that were registered in the 57system with `dump` request of ``DPLL_CMD_PIN_GET`` command. 58Configuration of a pin can be changed by `do` request of netlink 59``DPLL_CMD_PIN_SET`` command. 60Pin handle is a ``DPLL_A_PIN_ID``, it shall be provided to get or set 61configuration of particular pin in the system. It can be obtained with 62``DPLL_CMD_PIN_GET`` `dump` request or ``DPLL_CMD_PIN_ID_GET`` `do` 63request, where user provides attributes that result in single pin match. 64 65Pin selection 66============= 67 68In general, selected pin (the one which signal is driving the dpll 69device) can be obtained from ``DPLL_A_PIN_STATE`` attribute, and only 70one pin shall be in ``DPLL_PIN_STATE_CONNECTED`` state for any dpll 71device. 72 73Pin selection can be done either manually or automatically, depending 74on hardware capabilities and active dpll device work mode 75(``DPLL_A_MODE`` attribute). The consequence is that there are 76differences for each mode in terms of available pin states, as well as 77for the states the user can request for a dpll device. 78 79In manual mode (``DPLL_MODE_MANUAL``) the user can request or receive 80one of following pin states: 81 82- ``DPLL_PIN_STATE_CONNECTED`` - the pin is used to drive dpll device 83- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin is not used to drive dpll 84 device 85 86In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can request or 87receive one of following pin states: 88 89- ``DPLL_PIN_STATE_SELECTABLE`` - the pin shall be considered as valid 90 input for automatic selection algorithm 91- ``DPLL_PIN_STATE_DISCONNECTED`` - the pin shall be not considered as 92 a valid input for automatic selection algorithm 93 94In automatic mode (``DPLL_MODE_AUTOMATIC``) the user can only receive 95pin state ``DPLL_PIN_STATE_CONNECTED`` once automatic selection 96algorithm locks a dpll device with one of the inputs. 97 98Shared pins 99=========== 100 101A single pin object can be attached to multiple dpll devices. 102Then there are two groups of configuration knobs: 103 1041) Set on a pin - the configuration affects all dpll devices pin is 105 registered to (i.e., ``DPLL_A_PIN_FREQUENCY``), 1062) Set on a pin-dpll tuple - the configuration affects only selected 107 dpll device (i.e., ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE``, 108 ``DPLL_A_PIN_DIRECTION``). 109 110MUX-type pins 111============= 112 113A pin can be MUX-type, it aggregates child pins and serves as a pin 114multiplexer. One or more pins are registered with MUX-type instead of 115being directly registered to a dpll device. 116Pins registered with a MUX-type pin provide user with additional nested 117attribute ``DPLL_A_PIN_PARENT_PIN`` for each parent they were registered 118with. 119If a pin was registered with multiple parent pins, they behave like a 120multiple output multiplexer. In this case output of a 121``DPLL_CMD_PIN_GET`` would contain multiple pin-parent nested 122attributes with current state related to each parent, like:: 123 124 'pin': [{{ 125 'clock-id': 282574471561216, 126 'module-name': 'ice', 127 'capabilities': 4, 128 'id': 13, 129 'parent-pin': [ 130 {'parent-id': 2, 'state': 'connected'}, 131 {'parent-id': 3, 'state': 'disconnected'} 132 ], 133 'type': 'synce-eth-port' 134 }}] 135 136Only one child pin can provide its signal to the parent MUX-type pin at 137a time, the selection is done by requesting change of a child pin state 138on desired parent, with the use of ``DPLL_A_PIN_PARENT`` nested 139attribute. Example of netlink `set state on parent pin` message format: 140 141 ========================== ============================================= 142 ``DPLL_A_PIN_ID`` child pin id 143 ``DPLL_A_PIN_PARENT_PIN`` nested attribute for requesting configuration 144 related to parent pin 145 ``DPLL_A_PIN_PARENT_ID`` parent pin id 146 ``DPLL_A_PIN_STATE`` requested pin state on parent 147 ========================== ============================================= 148 149Pin priority 150============ 151 152Some devices might offer a capability of automatic pin selection mode 153(enum value ``DPLL_MODE_AUTOMATIC`` of ``DPLL_A_MODE`` attribute). 154Usually, automatic selection is performed on the hardware level, which 155means only pins directly connected to the dpll can be used for automatic 156input pin selection. 157In automatic selection mode, the user cannot manually select a input 158pin for the device, instead the user shall provide all directly 159connected pins with a priority ``DPLL_A_PIN_PRIO``, the device would 160pick a highest priority valid signal and use it to control the DPLL 161device. Example of netlink `set priority on parent pin` message format: 162 163 ============================ ============================================= 164 ``DPLL_A_PIN_ID`` configured pin id 165 ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting configuration 166 related to parent dpll device 167 ``DPLL_A_PIN_PARENT_ID`` parent dpll device id 168 ``DPLL_A_PIN_PRIO`` requested pin prio on parent dpll 169 ============================ ============================================= 170 171Child pin of MUX-type pin is not capable of automatic input pin selection, 172in order to configure active input of a MUX-type pin, the user needs to 173request desired pin state of the child pin on the parent pin, 174as described in the ``MUX-type pins`` chapter. 175 176Phase offset measurement and adjustment 177======================================== 178 179Device may provide ability to measure a phase difference between signals 180on a pin and its parent dpll device. If pin-dpll phase offset measurement 181is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET`` 182attribute for each parent dpll device. 183 184Device may also provide ability to adjust a signal phase on a pin. 185If pin phase adjustment is supported, minimal and maximal values that pin 186handle shall be provide to the user on ``DPLL_CMD_PIN_GET`` respond 187with ``DPLL_A_PIN_PHASE_ADJUST_MIN`` and ``DPLL_A_PIN_PHASE_ADJUST_MAX`` 188attributes. Configured phase adjust value is provided with 189``DPLL_A_PIN_PHASE_ADJUST`` attribute of a pin, and value change can be 190requested with the same attribute with ``DPLL_CMD_PIN_SET`` command. 191 192 =============================== ====================================== 193 ``DPLL_A_PIN_ID`` configured pin id 194 ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase adjustment 195 ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase adjustment 196 ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase 197 adjustment on parent dpll device 198 ``DPLL_A_PIN_PARENT_DEVICE`` nested attribute for requesting 199 configuration on given parent dpll 200 device 201 ``DPLL_A_PIN_PARENT_ID`` parent dpll device id 202 ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference 203 between a pin and parent dpll device 204 =============================== ====================================== 205 206All phase related values are provided in pico seconds, which represents 207time difference between signals phase. The negative value means that 208phase of signal on pin is earlier in time than dpll's signal. Positive 209value means that phase of signal on pin is later in time than signal of 210a dpll. 211 212Phase adjust (also min and max) values are integers, but measured phase 213offset values are fractional with 3-digit decimal places and shell be 214divided with ``DPLL_PIN_PHASE_OFFSET_DIVIDER`` to get integer part and 215modulo divided to get fractional part. 216 217Embedded SYNC 218============= 219 220Device may provide ability to use Embedded SYNC feature. It allows 221to embed additional SYNC signal into the base frequency of a pin - a one 222special pulse of base frequency signal every time SYNC signal pulse 223happens. The user can configure the frequency of Embedded SYNC. 224The Embedded SYNC capability is always related to a given base frequency 225and HW capabilities. The user is provided a range of Embedded SYNC 226frequencies supported, depending on current base frequency configured for 227the pin. 228 229 ========================================= ================================= 230 ``DPLL_A_PIN_ESYNC_FREQUENCY`` current Embedded SYNC frequency 231 ``DPLL_A_PIN_ESYNC_FREQUENCY_SUPPORTED`` nest available Embedded SYNC 232 frequency ranges 233 ``DPLL_A_PIN_FREQUENCY_MIN`` attr minimum value of frequency 234 ``DPLL_A_PIN_FREQUENCY_MAX`` attr maximum value of frequency 235 ``DPLL_A_PIN_ESYNC_PULSE`` pulse type of Embedded SYNC 236 ========================================= ================================= 237 238Configuration commands group 239============================ 240 241Configuration commands are used to get information about registered 242dpll devices (and pins), as well as set configuration of device or pins. 243As dpll devices must be abstracted and reflect real hardware, 244there is no way to add new dpll device via netlink from user space and 245each device should be registered by its driver. 246 247All netlink commands require ``GENL_ADMIN_PERM``. This is to prevent 248any spamming/DoS from unauthorized userspace applications. 249 250List of netlink commands with possible attributes 251================================================= 252 253Constants identifying command types for dpll device uses a 254``DPLL_CMD_`` prefix and suffix according to command purpose. 255The dpll device related attributes use a ``DPLL_A_`` prefix and 256suffix according to attribute purpose. 257 258 ==================================== ================================= 259 ``DPLL_CMD_DEVICE_ID_GET`` command to get device ID 260 ``DPLL_A_MODULE_NAME`` attr module name of registerer 261 ``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier 262 (EUI-64), as defined by the 263 IEEE 1588 standard 264 ``DPLL_A_TYPE`` attr type of dpll device 265 ==================================== ================================= 266 267 ==================================== ================================= 268 ``DPLL_CMD_DEVICE_GET`` command to get device info or 269 dump list of available devices 270 ``DPLL_A_ID`` attr unique dpll device ID 271 ``DPLL_A_MODULE_NAME`` attr module name of registerer 272 ``DPLL_A_CLOCK_ID`` attr Unique Clock Identifier 273 (EUI-64), as defined by the 274 IEEE 1588 standard 275 ``DPLL_A_MODE`` attr selection mode 276 ``DPLL_A_MODE_SUPPORTED`` attr available selection modes 277 ``DPLL_A_LOCK_STATUS`` attr dpll device lock status 278 ``DPLL_A_TEMP`` attr device temperature info 279 ``DPLL_A_TYPE`` attr type of dpll device 280 ==================================== ================================= 281 282 ==================================== ================================= 283 ``DPLL_CMD_DEVICE_SET`` command to set dpll device config 284 ``DPLL_A_ID`` attr internal dpll device index 285 ``DPLL_A_MODE`` attr selection mode to configure 286 ==================================== ================================= 287 288Constants identifying command types for pins uses a 289``DPLL_CMD_PIN_`` prefix and suffix according to command purpose. 290The pin related attributes use a ``DPLL_A_PIN_`` prefix and suffix 291according to attribute purpose. 292 293 ==================================== ================================= 294 ``DPLL_CMD_PIN_ID_GET`` command to get pin ID 295 ``DPLL_A_PIN_MODULE_NAME`` attr module name of registerer 296 ``DPLL_A_PIN_CLOCK_ID`` attr Unique Clock Identifier 297 (EUI-64), as defined by the 298 IEEE 1588 standard 299 ``DPLL_A_PIN_BOARD_LABEL`` attr pin board label provided 300 by registerer 301 ``DPLL_A_PIN_PANEL_LABEL`` attr pin panel label provided 302 by registerer 303 ``DPLL_A_PIN_PACKAGE_LABEL`` attr pin package label provided 304 by registerer 305 ``DPLL_A_PIN_TYPE`` attr type of a pin 306 ==================================== ================================= 307 308 ==================================== ================================== 309 ``DPLL_CMD_PIN_GET`` command to get pin info or dump 310 list of available pins 311 ``DPLL_A_PIN_ID`` attr unique a pin ID 312 ``DPLL_A_PIN_MODULE_NAME`` attr module name of registerer 313 ``DPLL_A_PIN_CLOCK_ID`` attr Unique Clock Identifier 314 (EUI-64), as defined by the 315 IEEE 1588 standard 316 ``DPLL_A_PIN_BOARD_LABEL`` attr pin board label provided 317 by registerer 318 ``DPLL_A_PIN_PANEL_LABEL`` attr pin panel label provided 319 by registerer 320 ``DPLL_A_PIN_PACKAGE_LABEL`` attr pin package label provided 321 by registerer 322 ``DPLL_A_PIN_TYPE`` attr type of a pin 323 ``DPLL_A_PIN_FREQUENCY`` attr current frequency of a pin 324 ``DPLL_A_PIN_FREQUENCY_SUPPORTED`` nested attr provides supported 325 frequencies 326 ``DPLL_A_PIN_ANY_FREQUENCY_MIN`` attr minimum value of frequency 327 ``DPLL_A_PIN_ANY_FREQUENCY_MAX`` attr maximum value of frequency 328 ``DPLL_A_PIN_PHASE_ADJUST_MIN`` attr minimum value of phase 329 adjustment 330 ``DPLL_A_PIN_PHASE_ADJUST_MAX`` attr maximum value of phase 331 adjustment 332 ``DPLL_A_PIN_PHASE_ADJUST`` attr configured value of phase 333 adjustment on parent device 334 ``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent device 335 the pin is connected with 336 ``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id 337 ``DPLL_A_PIN_PRIO`` attr priority of pin on the 338 dpll device 339 ``DPLL_A_PIN_STATE`` attr state of pin on the parent 340 dpll device 341 ``DPLL_A_PIN_DIRECTION`` attr direction of a pin on the 342 parent dpll device 343 ``DPLL_A_PIN_PHASE_OFFSET`` attr measured phase difference 344 between a pin and parent dpll 345 ``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin 346 the pin is connected with 347 ``DPLL_A_PIN_PARENT_ID`` attr parent pin id 348 ``DPLL_A_PIN_STATE`` attr state of pin on the parent 349 pin 350 ``DPLL_A_PIN_CAPABILITIES`` attr bitmask of pin capabilities 351 ==================================== ================================== 352 353 ==================================== ================================= 354 ``DPLL_CMD_PIN_SET`` command to set pins configuration 355 ``DPLL_A_PIN_ID`` attr unique a pin ID 356 ``DPLL_A_PIN_FREQUENCY`` attr requested frequency of a pin 357 ``DPLL_A_PIN_PHASE_ADJUST`` attr requested value of phase 358 adjustment on parent device 359 ``DPLL_A_PIN_PARENT_DEVICE`` nested attr for each parent dpll 360 device configuration request 361 ``DPLL_A_PIN_PARENT_ID`` attr parent dpll device id 362 ``DPLL_A_PIN_DIRECTION`` attr requested direction of a pin 363 ``DPLL_A_PIN_PRIO`` attr requested priority of pin on 364 the dpll device 365 ``DPLL_A_PIN_STATE`` attr requested state of pin on 366 the dpll device 367 ``DPLL_A_PIN_PARENT_PIN`` nested attr for each parent pin 368 configuration request 369 ``DPLL_A_PIN_PARENT_ID`` attr parent pin id 370 ``DPLL_A_PIN_STATE`` attr requested state of pin on 371 parent pin 372 ==================================== ================================= 373 374Netlink dump requests 375===================== 376 377The ``DPLL_CMD_DEVICE_GET`` and ``DPLL_CMD_PIN_GET`` commands are 378capable of dump type netlink requests, in which case the response is in 379the same format as for their ``do`` request, but every device or pin 380registered in the system is returned. 381 382SET commands format 383=================== 384 385``DPLL_CMD_DEVICE_SET`` - to target a dpll device, the user provides 386``DPLL_A_ID``, which is unique identifier of dpll device in the system, 387as well as parameter being configured (``DPLL_A_MODE``). 388 389``DPLL_CMD_PIN_SET`` - to target a pin user must provide a 390``DPLL_A_PIN_ID``, which is unique identifier of a pin in the system. 391Also configured pin parameters must be added. 392If ``DPLL_A_PIN_FREQUENCY`` is configured, this affects all the dpll 393devices that are connected with the pin, that is why frequency attribute 394shall not be enclosed in ``DPLL_A_PIN_PARENT_DEVICE``. 395Other attributes: ``DPLL_A_PIN_PRIO``, ``DPLL_A_PIN_STATE`` or 396``DPLL_A_PIN_DIRECTION`` must be enclosed in 397``DPLL_A_PIN_PARENT_DEVICE`` as their configuration relates to only one 398of parent dplls, targeted by ``DPLL_A_PIN_PARENT_ID`` attribute which is 399also required inside that nest. 400For MUX-type pins the ``DPLL_A_PIN_STATE`` attribute is configured in 401similar way, by enclosing required state in ``DPLL_A_PIN_PARENT_PIN`` 402nested attribute and targeted parent pin id in ``DPLL_A_PIN_PARENT_ID``. 403 404In general, it is possible to configure multiple parameters at once, but 405internally each parameter change will be invoked separately, where order 406of configuration is not guaranteed by any means. 407 408Configuration pre-defined enums 409=============================== 410 411.. kernel-doc:: include/uapi/linux/dpll.h 412 413Notifications 414============= 415 416dpll device can provide notifications regarding status changes of the 417device, i.e. lock status changes, input/output changes or other alarms. 418There is one multicast group that is used to notify user-space apps via 419netlink socket: ``DPLL_MCGRP_MONITOR`` 420 421Notifications messages: 422 423 ============================== ===================================== 424 ``DPLL_CMD_DEVICE_CREATE_NTF`` dpll device was created 425 ``DPLL_CMD_DEVICE_DELETE_NTF`` dpll device was deleted 426 ``DPLL_CMD_DEVICE_CHANGE_NTF`` dpll device has changed 427 ``DPLL_CMD_PIN_CREATE_NTF`` dpll pin was created 428 ``DPLL_CMD_PIN_DELETE_NTF`` dpll pin was deleted 429 ``DPLL_CMD_PIN_CHANGE_NTF`` dpll pin has changed 430 ============================== ===================================== 431 432Events format is the same as for the corresponding get command. 433Format of ``DPLL_CMD_DEVICE_`` events is the same as response of 434``DPLL_CMD_DEVICE_GET``. 435Format of ``DPLL_CMD_PIN_`` events is same as response of 436``DPLL_CMD_PIN_GET``. 437 438Device driver implementation 439============================ 440 441Device is allocated by dpll_device_get() call. Second call with the 442same arguments will not create new object but provides pointer to 443previously created device for given arguments, it also increases 444refcount of that object. 445Device is deallocated by dpll_device_put() call, which first 446decreases the refcount, once refcount is cleared the object is 447destroyed. 448 449Device should implement set of operations and register device via 450dpll_device_register() at which point it becomes available to the 451users. Multiple driver instances can obtain reference to it with 452dpll_device_get(), as well as register dpll device with their own 453ops and priv. 454 455The pins are allocated separately with dpll_pin_get(), it works 456similarly to dpll_device_get(). Function first creates object and then 457for each call with the same arguments only the object refcount 458increases. Also dpll_pin_put() works similarly to dpll_device_put(). 459 460A pin can be registered with parent dpll device or parent pin, depending 461on hardware needs. Each registration requires registerer to provide set 462of pin callbacks, and private data pointer for calling them: 463 464- dpll_pin_register() - register pin with a dpll device, 465- dpll_pin_on_pin_register() - register pin with another MUX type pin. 466 467Notifications of adding or removing dpll devices are created within 468subsystem itself. 469Notifications about registering/deregistering pins are also invoked by 470the subsystem. 471Notifications about status changes either of dpll device or a pin are 472invoked in two ways: 473 474- after successful change was requested on dpll subsystem, the subsystem 475 calls corresponding notification, 476- requested by device driver with dpll_device_change_ntf() or 477 dpll_pin_change_ntf() when driver informs about the status change. 478 479The device driver using dpll interface is not required to implement all 480the callback operation. Nevertheless, there are few required to be 481implemented. 482Required dpll device level callback operations: 483 484- ``.mode_get``, 485- ``.lock_status_get``. 486 487Required pin level callback operations: 488 489- ``.state_on_dpll_get`` (pins registered with dpll device), 490- ``.state_on_pin_get`` (pins registered with parent pin), 491- ``.direction_get``. 492 493Every other operation handler is checked for existence and 494``-EOPNOTSUPP`` is returned in case of absence of specific handler. 495 496The simplest implementation is in the OCP TimeCard driver. The ops 497structures are defined like this: 498 499.. code-block:: c 500 501 static const struct dpll_device_ops dpll_ops = { 502 .lock_status_get = ptp_ocp_dpll_lock_status_get, 503 .mode_get = ptp_ocp_dpll_mode_get, 504 .mode_supported = ptp_ocp_dpll_mode_supported, 505 }; 506 507 static const struct dpll_pin_ops dpll_pins_ops = { 508 .frequency_get = ptp_ocp_dpll_frequency_get, 509 .frequency_set = ptp_ocp_dpll_frequency_set, 510 .direction_get = ptp_ocp_dpll_direction_get, 511 .direction_set = ptp_ocp_dpll_direction_set, 512 .state_on_dpll_get = ptp_ocp_dpll_state_get, 513 }; 514 515The registration part is then looks like this part: 516 517.. code-block:: c 518 519 clkid = pci_get_dsn(pdev); 520 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE); 521 if (IS_ERR(bp->dpll)) { 522 err = PTR_ERR(bp->dpll); 523 dev_err(&pdev->dev, "dpll_device_alloc failed\n"); 524 goto out; 525 } 526 527 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp); 528 if (err) 529 goto out; 530 531 for (i = 0; i < OCP_SMA_NUM; i++) { 532 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop); 533 if (IS_ERR(bp->sma[i].dpll_pin)) { 534 err = PTR_ERR(bp->dpll); 535 goto out_dpll; 536 } 537 538 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, 539 &bp->sma[i]); 540 if (err) { 541 dpll_pin_put(bp->sma[i].dpll_pin); 542 goto out_dpll; 543 } 544 } 545 546In the error path we have to rewind every allocation in the reverse order: 547 548.. code-block:: c 549 550 while (i) { 551 --i; 552 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]); 553 dpll_pin_put(bp->sma[i].dpll_pin); 554 } 555 dpll_device_put(bp->dpll); 556 557More complex example can be found in Intel's ICE driver or nVidia's mlx5 driver. 558 559SyncE enablement 560================ 561For SyncE enablement it is required to allow control over dpll device 562for a software application which monitors and configures the inputs of 563dpll device in response to current state of a dpll device and its 564inputs. 565In such scenario, dpll device input signal shall be also configurable 566to drive dpll with signal recovered from the PHY netdevice. 567This is done by exposing a pin to the netdevice - attaching pin to the 568netdevice itself with 569``dpll_netdev_pin_set(struct net_device *dev, struct dpll_pin *dpll_pin)``. 570Exposed pin id handle ``DPLL_A_PIN_ID`` is then identifiable by the user 571as it is attached to rtnetlink respond to get ``RTM_NEWLINK`` command in 572nested attribute ``IFLA_DPLL_PIN``. 573