1 Bindings for specific devices: 2 3 i) Xilinx ML300 Framebuffer 4 5 Simple framebuffer device from the ML300 reference design (also on the 6 ML403 reference design as well as others). 7 8 Optional properties: 9 - resolution = <xres yres> : pixel resolution of framebuffer. Some 10 implementations use a different resolution. 11 Default is <d#640 d#480> 12 - virt-resolution = <xvirt yvirt> : Size of framebuffer in memory. 13 Default is <d#1024 d#480>. 14 - rotate-display (empty) : rotate display 180 degrees. 15 16 v) Xilinx hwicap 17 18 Xilinx hwicap devices provide access to the configuration logic 19 of the FPGA through the Internal Configuration Access Port 20 (ICAP). The ICAP enables partial reconfiguration of the FPGA, 21 readback of the configuration information, and some control over 22 'warm boots' of the FPGA fabric. 23 24 Required properties: 25 - xlnx,family : The family of the FPGA, necessary since the 26 capabilities of the underlying ICAP hardware 27 differ between different families. May be 28 'virtex2p', 'virtex4', or 'virtex5'. 29 - compatible : should contain "xlnx,xps-hwicap-1.00.a" or 30 "xlnx,opb-hwicap-1.00.b". 31 32 vii) Xilinx USB Host controller 33 34 The Xilinx USB host controller is EHCI compatible but with a different 35 base address for the EHCI registers, and it is always a big-endian 36 USB Host controller. The hardware can be configured as high speed only, 37 or high speed/full speed hybrid. 38 39 Required properties: 40 - xlnx,support-usb-fs: A value 0 means the core is built as high speed 41 only. A value 1 means the core also supports 42 full speed devices. 43 44