xref: /linux/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml (revision ff124bbbca1d3a07fa1392ffdbbdeece71f68ece) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
8
9maintainers:
10  - Rajendra Nayak <quic_rjendra@quicinc.com>
11
12properties:
13  $nodename:
14    pattern: "^(watchdog|timer)@[0-9a-f]+$"
15
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - qcom,apss-wdt-glymur
21              - qcom,kpss-wdt-ipq4019
22              - qcom,apss-wdt-ipq5018
23              - qcom,apss-wdt-ipq5332
24              - qcom,apss-wdt-ipq5424
25              - qcom,apss-wdt-ipq9574
26              - qcom,apss-wdt-kaanapali
27              - qcom,apss-wdt-msm8226
28              - qcom,apss-wdt-msm8974
29              - qcom,apss-wdt-msm8994
30              - qcom,apss-wdt-qcm2290
31              - qcom,apss-wdt-qcs404
32              - qcom,apss-wdt-qcs615
33              - qcom,apss-wdt-qcs8300
34              - qcom,apss-wdt-sa8255p
35              - qcom,apss-wdt-sa8775p
36              - qcom,apss-wdt-sc7180
37              - qcom,apss-wdt-sc7280
38              - qcom,apss-wdt-sc8180x
39              - qcom,apss-wdt-sc8280xp
40              - qcom,apss-wdt-sdm845
41              - qcom,apss-wdt-sdx55
42              - qcom,apss-wdt-sdx65
43              - qcom,apss-wdt-sm6115
44              - qcom,apss-wdt-sm6350
45              - qcom,apss-wdt-sm8150
46              - qcom,apss-wdt-sm8250
47              - qcom,apss-wdt-x1e80100
48          - const: qcom,kpss-wdt
49      - const: qcom,kpss-wdt
50        deprecated: true
51      - items:
52          - const: qcom,scss-timer
53          - const: qcom,msm-timer
54      - items:
55          - enum:
56              - qcom,kpss-wdt-apq8064
57              - qcom,kpss-wdt-ipq8064
58              - qcom,kpss-wdt-mdm9615
59              - qcom,kpss-wdt-msm8960
60          - const: qcom,kpss-timer
61          - const: qcom,msm-timer
62
63  reg:
64    maxItems: 1
65
66  clocks:
67    maxItems: 1
68
69  clock-names:
70    items:
71      - const: sleep
72
73  clock-frequency:
74    description:
75      The frequency of the general purpose timer in Hz.
76
77  cpu-offset:
78    $ref: /schemas/types.yaml#/definitions/uint32
79    description:
80      Per-CPU offset used when the timer is accessed without the CPU remapping
81      facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
82
83  interrupts:
84    minItems: 1
85    maxItems: 5
86
87required:
88  - compatible
89  - reg
90  - clocks
91
92allOf:
93  - $ref: watchdog.yaml#
94
95  - if:
96      properties:
97        compatible:
98          contains:
99            const: qcom,kpss-wdt
100    then:
101      properties:
102        clock-frequency: false
103        cpu-offset: false
104        interrupts:
105          minItems: 1
106          items:
107            - description: Bark
108            - description: Bite
109
110    else:
111      properties:
112        interrupts:
113          minItems: 3
114          items:
115            - description: Debug
116            - description: First general purpose timer
117            - description: Second general purpose timer
118            - description: First watchdog
119            - description: Second watchdog
120      required:
121        - clock-frequency
122
123unevaluatedProperties: false
124
125examples:
126  - |
127    #include <dt-bindings/interrupt-controller/arm-gic.h>
128
129    watchdog@17c10000 {
130        compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
131        reg = <0x17c10000 0x1000>;
132        clocks = <&sleep_clk>;
133        interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
134        timeout-sec = <10>;
135    };
136
137  - |
138    #include <dt-bindings/interrupt-controller/arm-gic.h>
139
140    watchdog@200a000 {
141        compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
142        interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
143                     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
144                     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
145                     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
146                     <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
147        reg = <0x0200a000 0x100>;
148        clock-frequency = <25000000>;
149        clocks = <&sleep_clk>;
150        clock-names = "sleep";
151        cpu-offset = <0x80000>;
152    };
153