xref: /linux/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml (revision d30c1683aaecb93d2ab95685dc4300a33d3cea7a) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
8
9maintainers:
10  - Rajendra Nayak <quic_rjendra@quicinc.com>
11
12properties:
13  $nodename:
14    pattern: "^(watchdog|timer)@[0-9a-f]+$"
15
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - qcom,kpss-wdt-ipq4019
21              - qcom,apss-wdt-ipq5018
22              - qcom,apss-wdt-ipq5332
23              - qcom,apss-wdt-ipq5424
24              - qcom,apss-wdt-ipq9574
25              - qcom,apss-wdt-kaanapali
26              - qcom,apss-wdt-msm8226
27              - qcom,apss-wdt-msm8974
28              - qcom,apss-wdt-msm8994
29              - qcom,apss-wdt-qcm2290
30              - qcom,apss-wdt-qcs404
31              - qcom,apss-wdt-qcs615
32              - qcom,apss-wdt-qcs8300
33              - qcom,apss-wdt-sa8255p
34              - qcom,apss-wdt-sa8775p
35              - qcom,apss-wdt-sc7180
36              - qcom,apss-wdt-sc7280
37              - qcom,apss-wdt-sc8180x
38              - qcom,apss-wdt-sc8280xp
39              - qcom,apss-wdt-sdm845
40              - qcom,apss-wdt-sdx55
41              - qcom,apss-wdt-sdx65
42              - qcom,apss-wdt-sm6115
43              - qcom,apss-wdt-sm6350
44              - qcom,apss-wdt-sm8150
45              - qcom,apss-wdt-sm8250
46          - const: qcom,kpss-wdt
47      - const: qcom,kpss-wdt
48        deprecated: true
49      - items:
50          - const: qcom,scss-timer
51          - const: qcom,msm-timer
52      - items:
53          - enum:
54              - qcom,kpss-wdt-apq8064
55              - qcom,kpss-wdt-ipq8064
56              - qcom,kpss-wdt-mdm9615
57              - qcom,kpss-wdt-msm8960
58          - const: qcom,kpss-timer
59          - const: qcom,msm-timer
60
61  reg:
62    maxItems: 1
63
64  clocks:
65    maxItems: 1
66
67  clock-names:
68    items:
69      - const: sleep
70
71  clock-frequency:
72    description:
73      The frequency of the general purpose timer in Hz.
74
75  cpu-offset:
76    $ref: /schemas/types.yaml#/definitions/uint32
77    description:
78      Per-CPU offset used when the timer is accessed without the CPU remapping
79      facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
80
81  interrupts:
82    minItems: 1
83    maxItems: 5
84
85required:
86  - compatible
87  - reg
88  - clocks
89
90allOf:
91  - $ref: watchdog.yaml#
92
93  - if:
94      properties:
95        compatible:
96          contains:
97            const: qcom,kpss-wdt
98    then:
99      properties:
100        clock-frequency: false
101        cpu-offset: false
102        interrupts:
103          minItems: 1
104          items:
105            - description: Bark
106            - description: Bite
107
108    else:
109      properties:
110        interrupts:
111          minItems: 3
112          items:
113            - description: Debug
114            - description: First general purpose timer
115            - description: Second general purpose timer
116            - description: First watchdog
117            - description: Second watchdog
118      required:
119        - clock-frequency
120
121unevaluatedProperties: false
122
123examples:
124  - |
125    #include <dt-bindings/interrupt-controller/arm-gic.h>
126
127    watchdog@17c10000 {
128        compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
129        reg = <0x17c10000 0x1000>;
130        clocks = <&sleep_clk>;
131        interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
132        timeout-sec = <10>;
133    };
134
135  - |
136    #include <dt-bindings/interrupt-controller/arm-gic.h>
137
138    watchdog@200a000 {
139        compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
140        interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
141                     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
142                     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
143                     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
144                     <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
145        reg = <0x0200a000 0x100>;
146        clock-frequency = <25000000>;
147        clocks = <&sleep_clk>;
148        clock-names = "sleep";
149        cpu-offset = <0x80000>;
150    };
151