xref: /linux/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml (revision 79d2e1919a2728ef49d938eb20ebd5903c14dfb0) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
8
9maintainers:
10  - Rajendra Nayak <quic_rjendra@quicinc.com>
11
12properties:
13  $nodename:
14    pattern: "^(watchdog|timer)@[0-9a-f]+$"
15
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - qcom,kpss-wdt-ipq4019
21              - qcom,apss-wdt-ipq5018
22              - qcom,apss-wdt-ipq5332
23              - qcom,apss-wdt-ipq9574
24              - qcom,apss-wdt-msm8226
25              - qcom,apss-wdt-msm8974
26              - qcom,apss-wdt-msm8994
27              - qcom,apss-wdt-qcm2290
28              - qcom,apss-wdt-qcs404
29              - qcom,apss-wdt-qcs615
30              - qcom,apss-wdt-qcs8300
31              - qcom,apss-wdt-sa8255p
32              - qcom,apss-wdt-sa8775p
33              - qcom,apss-wdt-sc7180
34              - qcom,apss-wdt-sc7280
35              - qcom,apss-wdt-sc8180x
36              - qcom,apss-wdt-sc8280xp
37              - qcom,apss-wdt-sdm845
38              - qcom,apss-wdt-sdx55
39              - qcom,apss-wdt-sdx65
40              - qcom,apss-wdt-sm6115
41              - qcom,apss-wdt-sm6350
42              - qcom,apss-wdt-sm8150
43              - qcom,apss-wdt-sm8250
44          - const: qcom,kpss-wdt
45      - const: qcom,kpss-wdt
46        deprecated: true
47      - items:
48          - const: qcom,scss-timer
49          - const: qcom,msm-timer
50      - items:
51          - enum:
52              - qcom,kpss-wdt-apq8064
53              - qcom,kpss-wdt-ipq8064
54              - qcom,kpss-wdt-mdm9615
55              - qcom,kpss-wdt-msm8960
56          - const: qcom,kpss-timer
57          - const: qcom,msm-timer
58
59  reg:
60    maxItems: 1
61
62  clocks:
63    maxItems: 1
64
65  clock-names:
66    items:
67      - const: sleep
68
69  clock-frequency:
70    description:
71      The frequency of the general purpose timer in Hz.
72
73  cpu-offset:
74    $ref: /schemas/types.yaml#/definitions/uint32
75    description:
76      Per-CPU offset used when the timer is accessed without the CPU remapping
77      facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
78
79  interrupts:
80    minItems: 1
81    maxItems: 5
82
83required:
84  - compatible
85  - reg
86  - clocks
87
88allOf:
89  - $ref: watchdog.yaml#
90
91  - if:
92      properties:
93        compatible:
94          contains:
95            const: qcom,kpss-wdt
96    then:
97      properties:
98        clock-frequency: false
99        cpu-offset: false
100        interrupts:
101          minItems: 1
102          items:
103            - description: Bark
104            - description: Bite
105
106    else:
107      properties:
108        interrupts:
109          minItems: 3
110          items:
111            - description: Debug
112            - description: First general purpose timer
113            - description: Second general purpose timer
114            - description: First watchdog
115            - description: Second watchdog
116      required:
117        - clock-frequency
118
119unevaluatedProperties: false
120
121examples:
122  - |
123    #include <dt-bindings/interrupt-controller/arm-gic.h>
124
125    watchdog@17c10000 {
126        compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
127        reg = <0x17c10000 0x1000>;
128        clocks = <&sleep_clk>;
129        interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
130        timeout-sec = <10>;
131    };
132
133  - |
134    #include <dt-bindings/interrupt-controller/arm-gic.h>
135
136    watchdog@200a000 {
137        compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
138        interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
139                     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
140                     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
141                     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
142                     <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
143        reg = <0x0200a000 0x100>;
144        clock-frequency = <25000000>;
145        clocks = <&sleep_clk>;
146        clock-names = "sleep";
147        cpu-offset = <0x80000>;
148    };
149