xref: /linux/Documentation/devicetree/bindings/watchdog/qcom-wdt.yaml (revision 26b8eb8a98c18b2ee4ea76d99fa2b2a5ccbc1b6c) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/watchdog/qcom-wdt.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm Krait Processor Sub-system (KPSS) Watchdog timer
8
9maintainers:
10  - Rajendra Nayak <quic_rjendra@quicinc.com>
11
12properties:
13  $nodename:
14    pattern: "^(watchdog|timer)@[0-9a-f]+$"
15
16  compatible:
17    oneOf:
18      - items:
19          - enum:
20              - qcom,apss-wdt-glymur
21              - qcom,apss-wdt-hawi
22              - qcom,kpss-wdt-ipq4019
23              - qcom,apss-wdt-ipq5018
24              - qcom,apss-wdt-ipq5210
25              - qcom,apss-wdt-ipq5332
26              - qcom,apss-wdt-ipq5424
27              - qcom,apss-wdt-ipq9574
28              - qcom,apss-wdt-ipq9650
29              - qcom,apss-wdt-kaanapali
30              - qcom,apss-wdt-msm8226
31              - qcom,apss-wdt-msm8974
32              - qcom,apss-wdt-msm8994
33              - qcom,apss-wdt-nord
34              - qcom,apss-wdt-qcm2290
35              - qcom,apss-wdt-qcs404
36              - qcom,apss-wdt-qcs615
37              - qcom,apss-wdt-qcs8300
38              - qcom,apss-wdt-sa8255p
39              - qcom,apss-wdt-sa8775p
40              - qcom,apss-wdt-sc7180
41              - qcom,apss-wdt-sc7280
42              - qcom,apss-wdt-sc8180x
43              - qcom,apss-wdt-sc8280xp
44              - qcom,apss-wdt-sdm845
45              - qcom,apss-wdt-sdx55
46              - qcom,apss-wdt-sdx65
47              - qcom,apss-wdt-shikra
48              - qcom,apss-wdt-sm6115
49              - qcom,apss-wdt-sm6350
50              - qcom,apss-wdt-sm8150
51              - qcom,apss-wdt-sm8250
52              - qcom,apss-wdt-x1e80100
53          - const: qcom,kpss-wdt
54      - const: qcom,kpss-wdt
55        deprecated: true
56      - items:
57          - const: qcom,scss-timer
58          - const: qcom,msm-timer
59      - items:
60          - enum:
61              - qcom,kpss-wdt-apq8064
62              - qcom,kpss-wdt-ipq8064
63              - qcom,kpss-wdt-mdm9615
64              - qcom,kpss-wdt-msm8960
65          - const: qcom,kpss-timer
66          - const: qcom,msm-timer
67
68  reg:
69    maxItems: 1
70
71  clocks:
72    maxItems: 1
73
74  clock-names:
75    items:
76      - const: sleep
77
78  clock-frequency:
79    description:
80      The frequency of the general purpose timer in Hz.
81
82  cpu-offset:
83    $ref: /schemas/types.yaml#/definitions/uint32
84    description:
85      Per-CPU offset used when the timer is accessed without the CPU remapping
86      facilities. The offset is cpu-offset + (0x10000 * cpu-nr).
87
88  interrupts:
89    minItems: 1
90    maxItems: 5
91
92  sram:
93    maxItems: 1
94    description:
95      A reference to an region residing in IMEM(on-chip SRAM), which contains
96      the system restart reason value populated by the bootloader.
97
98required:
99  - compatible
100  - reg
101  - clocks
102
103allOf:
104  - $ref: watchdog.yaml#
105
106  - if:
107      properties:
108        compatible:
109          contains:
110            const: qcom,kpss-wdt
111    then:
112      properties:
113        clock-frequency: false
114        cpu-offset: false
115        interrupts:
116          minItems: 1
117          items:
118            - description: Bark
119            - description: Bite
120
121    else:
122      properties:
123        interrupts:
124          minItems: 3
125          items:
126            - description: Debug
127            - description: First general purpose timer
128            - description: Second general purpose timer
129            - description: First watchdog
130            - description: Second watchdog
131      required:
132        - clock-frequency
133
134unevaluatedProperties: false
135
136examples:
137  - |
138    #include <dt-bindings/interrupt-controller/arm-gic.h>
139
140    watchdog@17c10000 {
141        compatible = "qcom,apss-wdt-sm8150", "qcom,kpss-wdt";
142        reg = <0x17c10000 0x1000>;
143        clocks = <&sleep_clk>;
144        interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>;
145        timeout-sec = <10>;
146    };
147
148  - |
149    #include <dt-bindings/interrupt-controller/arm-gic.h>
150
151    watchdog@200a000 {
152        compatible = "qcom,kpss-wdt-ipq8064", "qcom,kpss-timer", "qcom,msm-timer";
153        interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
154                     <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
155                     <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
156                     <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>,
157                     <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
158        reg = <0x0200a000 0x100>;
159        clock-frequency = <25000000>;
160        clocks = <&sleep_clk>;
161        clock-names = "sleep";
162        cpu-offset = <0x80000>;
163    };
164