1*c703ba72SUdaya Kiran Challa# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*c703ba72SUdaya Kiran Challa%YAML 1.2 3*c703ba72SUdaya Kiran Challa--- 4*c703ba72SUdaya Kiran Challa$id: http://devicetree.org/schemas/watchdog/microchip,pic32mzda-dmt.yaml# 5*c703ba72SUdaya Kiran Challa$schema: http://devicetree.org/meta-schemas/core.yaml# 6*c703ba72SUdaya Kiran Challa 7*c703ba72SUdaya Kiran Challatitle: Microchip PIC32MZDA Deadman Timer 8*c703ba72SUdaya Kiran Challa 9*c703ba72SUdaya Kiran Challamaintainers: 10*c703ba72SUdaya Kiran Challa - Thomas Bogendoerfer <tsbogend@alpha.franken.de> 11*c703ba72SUdaya Kiran Challa 12*c703ba72SUdaya Kiran Challadescription: | 13*c703ba72SUdaya Kiran Challa The deadman timer is used to reset the processor in the event of a software 14*c703ba72SUdaya Kiran Challa malfunction. It is a free-running instruction fetch timer, which is clocked 15*c703ba72SUdaya Kiran Challa whenever an instruction fetch occurs until a count match occurs. 16*c703ba72SUdaya Kiran Challa 17*c703ba72SUdaya Kiran ChallaallOf: 18*c703ba72SUdaya Kiran Challa - $ref: watchdog.yaml# 19*c703ba72SUdaya Kiran Challa 20*c703ba72SUdaya Kiran Challaproperties: 21*c703ba72SUdaya Kiran Challa compatible: 22*c703ba72SUdaya Kiran Challa const: microchip,pic32mzda-dmt 23*c703ba72SUdaya Kiran Challa 24*c703ba72SUdaya Kiran Challa reg: 25*c703ba72SUdaya Kiran Challa maxItems: 1 26*c703ba72SUdaya Kiran Challa 27*c703ba72SUdaya Kiran Challa clocks: 28*c703ba72SUdaya Kiran Challa maxItems: 1 29*c703ba72SUdaya Kiran Challa 30*c703ba72SUdaya Kiran Challarequired: 31*c703ba72SUdaya Kiran Challa - compatible 32*c703ba72SUdaya Kiran Challa - reg 33*c703ba72SUdaya Kiran Challa - clocks 34*c703ba72SUdaya Kiran Challa 35*c703ba72SUdaya Kiran ChallaunevaluatedProperties: false 36*c703ba72SUdaya Kiran Challa 37*c703ba72SUdaya Kiran Challaexamples: 38*c703ba72SUdaya Kiran Challa - | 39*c703ba72SUdaya Kiran Challa #include <dt-bindings/clock/microchip,pic32-clock.h> 40*c703ba72SUdaya Kiran Challa 41*c703ba72SUdaya Kiran Challa watchdog@1f800a00 { 42*c703ba72SUdaya Kiran Challa compatible = "microchip,pic32mzda-dmt"; 43*c703ba72SUdaya Kiran Challa reg = <0x1f800a00 0x80>; 44*c703ba72SUdaya Kiran Challa clocks = <&rootclk PB7CLK>; 45*c703ba72SUdaya Kiran Challa }; 46