xref: /linux/Documentation/devicetree/bindings/watchdog/arm,sp805.yaml (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
173d3e43fSAndre Przywara# SPDX-License-Identifier: GPL-2.0
273d3e43fSAndre Przywara%YAML 1.2
373d3e43fSAndre Przywara---
473d3e43fSAndre Przywara$id: http://devicetree.org/schemas/watchdog/arm,sp805.yaml#
573d3e43fSAndre Przywara$schema: http://devicetree.org/meta-schemas/core.yaml#
673d3e43fSAndre Przywara
773d3e43fSAndre Przywaratitle: ARM AMBA Primecell SP805 Watchdog
873d3e43fSAndre Przywara
973d3e43fSAndre Przywaramaintainers:
1073d3e43fSAndre Przywara  - Viresh Kumar <vireshk@kernel.org>
1173d3e43fSAndre Przywara
1273d3e43fSAndre Przywaradescription: |+
1373d3e43fSAndre Przywara  The Arm SP805 IP implements a watchdog device, which triggers an interrupt
1473d3e43fSAndre Przywara  after a configurable time period. If that interrupt has not been serviced
1573d3e43fSAndre Przywara  when the next interrupt would be triggered, the reset signal is asserted.
1673d3e43fSAndre Przywara
1773d3e43fSAndre PrzywaraallOf:
1873d3e43fSAndre Przywara  - $ref: /schemas/watchdog/watchdog.yaml#
1973d3e43fSAndre Przywara
2073d3e43fSAndre Przywara# Need a custom select here or 'arm,primecell' will match on lots of nodes
2173d3e43fSAndre Przywaraselect:
2273d3e43fSAndre Przywara  properties:
2373d3e43fSAndre Przywara    compatible:
2473d3e43fSAndre Przywara      contains:
2573d3e43fSAndre Przywara        const: arm,sp805
2673d3e43fSAndre Przywara  required:
2773d3e43fSAndre Przywara    - compatible
2873d3e43fSAndre Przywara
2973d3e43fSAndre Przywaraproperties:
3073d3e43fSAndre Przywara  compatible:
3173d3e43fSAndre Przywara    items:
3273d3e43fSAndre Przywara      - const: arm,sp805
3373d3e43fSAndre Przywara      - const: arm,primecell
3473d3e43fSAndre Przywara
3573d3e43fSAndre Przywara  interrupts:
3673d3e43fSAndre Przywara    maxItems: 1
3773d3e43fSAndre Przywara
3873d3e43fSAndre Przywara  reg:
3973d3e43fSAndre Przywara    maxItems: 1
4073d3e43fSAndre Przywara
4173d3e43fSAndre Przywara  clocks:
4273d3e43fSAndre Przywara    description: |
4373d3e43fSAndre Przywara      Clocks driving the watchdog timer hardware. The first clock is used
4473d3e43fSAndre Przywara      for the actual watchdog counter. The second clock drives the register
4573d3e43fSAndre Przywara      interface.
4673d3e43fSAndre Przywara    maxItems: 2
4773d3e43fSAndre Przywara
4873d3e43fSAndre Przywara  clock-names:
4973d3e43fSAndre Przywara    items:
5073d3e43fSAndre Przywara      - const: wdog_clk
5173d3e43fSAndre Przywara      - const: apb_pclk
5273d3e43fSAndre Przywara
53*f4c53582SYang Xiwen  resets:
54*f4c53582SYang Xiwen    maxItems: 1
55*f4c53582SYang Xiwen    description: WDOGRESn input reset signal for sp805 module.
56*f4c53582SYang Xiwen
5773d3e43fSAndre Przywararequired:
5873d3e43fSAndre Przywara  - compatible
5973d3e43fSAndre Przywara  - reg
6073d3e43fSAndre Przywara  - clocks
6173d3e43fSAndre Przywara  - clock-names
6273d3e43fSAndre Przywara
6373d3e43fSAndre PrzywaraunevaluatedProperties: false
6473d3e43fSAndre Przywara
6573d3e43fSAndre Przywaraexamples:
6673d3e43fSAndre Przywara  - |
6773d3e43fSAndre Przywara    #include <dt-bindings/interrupt-controller/arm-gic.h>
6873d3e43fSAndre Przywara    watchdog@66090000 {
6973d3e43fSAndre Przywara        compatible = "arm,sp805", "arm,primecell";
7073d3e43fSAndre Przywara        reg = <0x66090000 0x1000>;
7173d3e43fSAndre Przywara        interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>;
7273d3e43fSAndre Przywara        clocks = <&wdt_clk>, <&apb_pclk>;
7373d3e43fSAndre Przywara        clock-names = "wdog_clk", "apb_pclk";
74*f4c53582SYang Xiwen        resets = <&wdt_rst>;
7573d3e43fSAndre Przywara    };
76