xref: /linux/Documentation/devicetree/bindings/virtio/pci-iommu.yaml (revision 4b132aacb0768ac1e652cf517097ea6f237214b9) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: virtio-iommu device using the virtio-pci transport
8
9maintainers:
10  - Jean-Philippe Brucker <jean-philippe@linaro.org>
11
12description: |
13  When virtio-iommu uses the PCI transport, its programming interface is
14  discovered dynamically by the PCI probing infrastructure. However the
15  device tree statically describes the relation between IOMMU and DMA
16  masters. Therefore, the PCI root complex that hosts the virtio-iommu
17  contains a child node representing the IOMMU device explicitly.
18
19  DMA from the IOMMU device isn't managed by another IOMMU. Therefore the
20  virtio-iommu node doesn't have an "iommus" property, and is omitted from
21  the iommu-map property of the root complex.
22
23properties:
24  # If compatible is present, it should contain the vendor and device ID
25  # according to the PCI Bus Binding specification. Since PCI provides
26  # built-in identification methods, compatible is not actually required.
27  compatible:
28    oneOf:
29      - items:
30          - const: virtio,pci-iommu
31          - const: pci1af4,1057
32      - items:
33          - const: pci1af4,1057
34
35  reg:
36    description: |
37      PCI address of the IOMMU. As defined in the PCI Bus Binding
38      reference, the reg property is a five-cell address encoded as (phys.hi
39      phys.mid phys.lo size.hi size.lo). phys.hi should contain the device's
40      BDF as 0b00000000 bbbbbbbb dddddfff 00000000. The other cells should be
41      zero. See Documentation/devicetree/bindings/pci/pci.txt
42
43  '#iommu-cells':
44    const: 1
45
46required:
47  - compatible
48  - reg
49  - '#iommu-cells'
50
51additionalProperties: false
52
53examples:
54  - |
55    bus {
56        #address-cells = <2>;
57        #size-cells = <2>;
58
59        pcie@40000000 {
60            device_type = "pci";
61            #address-cells = <3>;
62            #size-cells = <2>;
63            reg = <0x0 0x40000000  0x0 0x1000000>;
64            ranges = <0x02000000 0x0 0x41000000  0x0 0x41000000  0x0 0x0f000000>;
65
66            /*
67             * The IOMMU manages all functions in this PCI domain except
68             * itself. Omit BDF 00:01.0.
69             */
70            iommu-map = <0x0 &iommu0 0x0 0x8
71                         0x9 &iommu0 0x9 0xfff7>;
72
73            /* The IOMMU programming interface uses slot 00:01.0 */
74            iommu0: iommu@1,0 {
75                compatible = "pci1af4,1057";
76                reg = <0x800 0 0 0 0>;
77                #iommu-cells = <1>;
78            };
79        };
80
81        pcie@50000000 {
82            device_type = "pci";
83            #address-cells = <3>;
84            #size-cells = <2>;
85            reg = <0x0 0x50000000  0x0 0x1000000>;
86            ranges = <0x02000000 0x0 0x51000000  0x0 0x51000000  0x0 0x0f000000>;
87
88            /*
89             * The IOMMU also manages all functions from this domain,
90             * with endpoint IDs 0x10000 - 0x1ffff
91             */
92            iommu-map = <0x0 &iommu0 0x10000 0x10000>;
93        };
94
95        ethernet {
96            /* The IOMMU manages this platform device with endpoint ID 0x20000 */
97            iommus = <&iommu0 0x20000>;
98        };
99    };
100
101...
102