xref: /linux/Documentation/devicetree/bindings/usb/ti,hd3ss3220.yaml (revision d30c1683aaecb93d2ab95685dc4300a33d3cea7a) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/ti,hd3ss3220.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: TI HD3SS3220 TypeC DRP Port Controller
8
9maintainers:
10  - Biju Das <biju.das.jz@bp.renesas.com>
11
12description: |-
13  HD3SS3220 is a USB SuperSpeed (SS) 2:1 mux with DRP port controller. The device provides Channel
14  Configuration (CC) logic and 5V VCONN sourcing for ecosystems implementing USB Type-C. The
15  HD3SS3220 can be configured as a Downstream Facing Port (DFP), Upstream Facing Port (UFP) or a
16  Dual Role Port (DRP) making it ideal for any application.
17
18properties:
19  compatible:
20    const: ti,hd3ss3220
21
22  reg:
23    maxItems: 1
24
25  interrupts:
26    maxItems: 1
27
28  id-gpios:
29    description:
30      An input gpio for USB ID pin. Upon detecting a UFP device, HD3SS3220
31      will keep ID pin high if VBUS is not at VSafe0V. Once VBUS is at VSafe0V,
32      the HD3SS3220 will assert ID pin low. This is done to enforce Type-C
33      requirement that VBUS must be at VSafe0V before re-enabling VBUS.
34    maxItems: 1
35
36  ports:
37    $ref: /schemas/graph.yaml#/properties/ports
38    description: OF graph bindings (specified in bindings/graph.txt) that model
39      SS data bus to the SS capable connector.
40
41    properties:
42      port@0:
43        $ref: /schemas/graph.yaml#/properties/port
44        description: Super Speed (SS) MUX inputs connected to SS capable connector.
45
46      port@1:
47        $ref: /schemas/graph.yaml#/properties/port
48        description: Output of 2:1 MUX connected to Super Speed (SS) data bus.
49
50    required:
51      - port@0
52      - port@1
53
54required:
55  - compatible
56  - reg
57
58additionalProperties: false
59
60examples:
61  - |
62    i2c {
63        #address-cells = <1>;
64        #size-cells = <0>;
65
66        hd3ss3220@47 {
67            compatible = "ti,hd3ss3220";
68            reg = <0x47>;
69            interrupt-parent = <&gpio6>;
70            interrupts = <3>;
71
72            ports {
73                #address-cells = <1>;
74                #size-cells = <0>;
75                port@0 {
76                    reg = <0>;
77                    hd3ss3220_in_ep: endpoint {
78                        remote-endpoint = <&ss_ep>;
79                    };
80                };
81                port@1 {
82                    reg = <1>;
83                    hd3ss3220_out_ep: endpoint {
84                        remote-endpoint = <&usb3_role_switch>;
85                    };
86                };
87            };
88        };
89    };
90