1# SPDX-License-Identifier: GPL-2.0 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/snps,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Synopsys DesignWare USB3 Controller 8 9maintainers: 10 - Felipe Balbi <balbi@kernel.org> 11 12description: 13 This is usually a subnode to DWC3 glue to which it is connected, but can also 14 be presented as a standalone DT node with an optional vendor-specific 15 compatible string. 16 17allOf: 18 - $ref: usb-drd.yaml# 19 - if: 20 properties: 21 dr_mode: 22 const: peripheral 23 24 required: 25 - dr_mode 26 then: 27 $ref: usb.yaml# 28 else: 29 $ref: usb-xhci.yaml# 30 31properties: 32 compatible: 33 contains: 34 oneOf: 35 - const: snps,dwc3 36 - const: synopsys,dwc3 37 deprecated: true 38 39 reg: 40 maxItems: 1 41 42 interrupts: 43 description: 44 It's either a single common DWC3 interrupt (dwc_usb3) or individual 45 interrupts for the host, gadget and DRD modes. 46 minItems: 1 47 maxItems: 4 48 49 interrupt-names: 50 minItems: 1 51 maxItems: 4 52 oneOf: 53 - const: dwc_usb3 54 - items: 55 enum: [host, peripheral, otg, wakeup] 56 57 clocks: 58 description: 59 In general the core supports three types of clocks. bus_early is a 60 SoC Bus Clock (AHB/AXI/Native). ref generates ITP when the UTMI/ULPI 61 PHY is suspended. suspend clocks a small part of the USB3 core when 62 SS PHY in P3. But particular cases may differ from that having less 63 or more clock sources with another names. 64 65 clock-names: 66 contains: 67 anyOf: 68 - enum: [bus_early, ref, suspend] 69 - true 70 71 dma-coherent: true 72 73 extcon: 74 maxItems: 1 75 deprecated: true 76 77 iommus: 78 maxItems: 1 79 80 usb-phy: 81 minItems: 1 82 items: 83 - description: USB2/HS PHY 84 - description: USB3/SS PHY 85 86 phys: 87 minItems: 1 88 maxItems: 19 89 90 phy-names: 91 minItems: 1 92 maxItems: 19 93 oneOf: 94 - items: 95 enum: [ usb2-phy, usb3-phy ] 96 - items: 97 pattern: "^usb(2-([0-9]|1[0-4])|3-[0-3])$" 98 99 power-domains: 100 description: 101 The DWC3 has 2 power-domains. The power management unit (PMU) and 102 everything else. The PMU is typically always powered and may not have an 103 entry. 104 minItems: 1 105 items: 106 - description: Core 107 - description: Power management unit 108 109 resets: 110 minItems: 1 111 112 snps,usb2-lpm-disable: 113 description: Indicate if we don't want to enable USB2 HW LPM for host 114 mode. 115 type: boolean 116 117 snps,usb3_lpm_capable: 118 description: Determines if platform is USB3 LPM capable 119 type: boolean 120 121 snps,usb2-gadget-lpm-disable: 122 description: Indicate if we don't want to enable USB2 HW LPM for gadget 123 mode. 124 type: boolean 125 126 snps,dis-start-transfer-quirk: 127 description: 128 When set, disable isoc START TRANSFER command failure SW work-around 129 for DWC_usb31 version 1.70a-ea06 and prior. 130 type: boolean 131 132 snps,disable_scramble_quirk: 133 description: 134 True when SW should disable data scrambling. Only really useful for FPGA 135 builds. 136 type: boolean 137 138 snps,has-lpm-erratum: 139 description: True when DWC3 was configured with LPM Erratum enabled 140 type: boolean 141 142 snps,lpm-nyet-threshold: 143 description: LPM NYET threshold 144 $ref: /schemas/types.yaml#/definitions/uint8 145 146 snps,u2exit_lfps_quirk: 147 description: Set if we want to enable u2exit lfps quirk 148 type: boolean 149 150 snps,u2ss_inp3_quirk: 151 description: Set if we enable P3 OK for U2/SS Inactive quirk 152 type: boolean 153 154 snps,req_p1p2p3_quirk: 155 description: 156 When set, the core will always request for P1/P2/P3 transition sequence. 157 type: boolean 158 159 snps,del_p1p2p3_quirk: 160 description: 161 When set core will delay P1/P2/P3 until a certain amount of 8B10B errors 162 occur. 163 type: boolean 164 165 snps,del_phy_power_chg_quirk: 166 description: When set core will delay PHY power change from P0 to P1/P2/P3. 167 type: boolean 168 169 snps,lfps_filter_quirk: 170 description: When set core will filter LFPS reception. 171 type: boolean 172 173 snps,rx_detect_poll_quirk: 174 description: 175 when set core will disable a 400us delay to start Polling LFPS after 176 RX.Detect. 177 type: boolean 178 179 snps,tx_de_emphasis_quirk: 180 description: When set core will set Tx de-emphasis value 181 type: boolean 182 183 snps,tx_de_emphasis: 184 description: 185 The value driven to the PHY is controlled by the LTSSM during USB3 186 Compliance mode. 187 $ref: /schemas/types.yaml#/definitions/uint8 188 enum: 189 - 0 # -6dB de-emphasis 190 - 1 # -3.5dB de-emphasis 191 - 2 # No de-emphasis 192 193 snps,dis_u3_susphy_quirk: 194 description: When set core will disable USB3 suspend phy 195 type: boolean 196 197 snps,dis_u2_susphy_quirk: 198 description: When set core will disable USB2 suspend phy 199 type: boolean 200 201 snps,dis_enblslpm_quirk: 202 description: 203 When set clears the enblslpm in GUSB2PHYCFG, disabling the suspend signal 204 to the PHY. 205 type: boolean 206 207 snps,dis-u1-entry-quirk: 208 description: Set if link entering into U1 needs to be disabled 209 type: boolean 210 211 snps,dis-u2-entry-quirk: 212 description: Set if link entering into U2 needs to be disabled 213 type: boolean 214 215 snps,dis_rxdet_inp3_quirk: 216 description: 217 When set core will disable receiver detection in PHY P3 power state. 218 type: boolean 219 220 snps,dis-u2-freeclk-exists-quirk: 221 description: 222 When set, clear the u2_freeclk_exists in GUSB2PHYCFG, specify that USB2 223 PHY doesn't provide a free-running PHY clock. 224 type: boolean 225 226 snps,dis-del-phy-power-chg-quirk: 227 description: 228 When set core will change PHY power from P0 to P1/P2/P3 without delay. 229 type: boolean 230 231 snps,dis-tx-ipgap-linecheck-quirk: 232 description: When set, disable u2mac linestate check during HS transmit 233 type: boolean 234 235 snps,parkmode-disable-ss-quirk: 236 description: 237 When set, all SuperSpeed bus instances in park mode are disabled. 238 type: boolean 239 240 snps,parkmode-disable-hs-quirk: 241 description: 242 When set, all HighSpeed bus instances in park mode are disabled. 243 type: boolean 244 245 snps,dis_metastability_quirk: 246 description: 247 When set, disable metastability workaround. CAUTION! Use only if you are 248 absolutely sure of it. 249 type: boolean 250 251 snps,dis-split-quirk: 252 description: 253 When set, change the way URBs are handled by the driver. Needed to 254 avoid -EPROTO errors with usbhid on some devices (Hikey 970). 255 type: boolean 256 257 snps,gfladj-refclk-lpm-sel-quirk: 258 description: 259 When set, run the SOF/ITP counter based on ref_clk. 260 type: boolean 261 262 snps,resume-hs-terminations: 263 description: 264 Fix the issue of HS terminations CRC error on resume by enabling this 265 quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end 266 of resume. This option is to support certain legacy ULPI PHYs. 267 type: boolean 268 269 snps,ulpi-ext-vbus-drv: 270 description: 271 Some ULPI USB PHY does not support internal VBUS supply, and driving 272 the CPEN pin, requires the configuration of the ulpi DRVVBUSEXTERNAL 273 bit. When set, the xhci host will configure the USB2 PHY drives VBUS 274 with an external supply. 275 type: boolean 276 277 snps,is-utmi-l1-suspend: 278 description: 279 True when DWC3 asserts output signal utmi_l1_suspend_n, false when 280 asserts utmi_sleep_n. 281 type: boolean 282 283 snps,hird-threshold: 284 description: HIRD threshold 285 $ref: /schemas/types.yaml#/definitions/uint8 286 287 snps,hsphy_interface: 288 description: 289 High-Speed PHY interface selection between UTMI+ and ULPI when the 290 DWC_USB3_HSPHY_INTERFACE has value 3. 291 $ref: /schemas/types.yaml#/definitions/string 292 enum: [utmi, ulpi] 293 294 snps,quirk-frame-length-adjustment: 295 description: 296 Value for GFLADJ_30MHZ field of GFLADJ register for post-silicon frame 297 length adjustment when the fladj_30mhz_sdbnd signal is invalid or 298 incorrect. 299 $ref: /schemas/types.yaml#/definitions/uint32 300 minimum: 0 301 maximum: 0x3f 302 303 snps,ref-clock-period-ns: 304 description: 305 Value for REFCLKPER field of GUCTL register for reference clock period in 306 nanoseconds, when the hardware set default does not match the actual 307 clock. 308 309 This binding is deprecated. Instead, provide an appropriate reference clock. 310 minimum: 8 311 maximum: 62 312 deprecated: true 313 314 snps,rx-thr-num-pkt: 315 description: 316 USB RX packet threshold count. In host mode, this field specifies 317 the space that must be available in the RX FIFO before the core can 318 start the corresponding USB RX transaction (burst). 319 In device mode, this field specifies the space that must be 320 available in the RX FIFO before the core can send ERDY for a 321 flow-controlled endpoint. It is only used for SuperSpeed. 322 The valid values for this field are from 1 to 15. (DWC3 SuperSpeed 323 USB 3.0 Controller Databook) 324 $ref: /schemas/types.yaml#/definitions/uint8 325 minimum: 1 326 maximum: 15 327 328 snps,rx-max-burst: 329 description: 330 Max USB RX burst size. In host mode, this field specifies the 331 Maximum Bulk IN burst the DWC_usb3 core can perform. When the system 332 bus is slower than the USB, RX FIFO can overrun during a long burst. 333 You can program a smaller value to this field to limit the RX burst 334 size that the core can perform. It only applies to SS Bulk, 335 Isochronous, and Interrupt IN endpoints in the host mode. 336 In device mode, this field specifies the NUMP value that is sent in 337 ERDY for an OUT endpoint. 338 The valid values for this field are from 1 to 16. (DWC3 SuperSpeed 339 USB 3.0 Controller Databook) 340 $ref: /schemas/types.yaml#/definitions/uint8 341 minimum: 1 342 maximum: 16 343 344 snps,tx-thr-num-pkt: 345 description: 346 USB TX packet threshold count. This field specifies the number of 347 packets that must be in the TXFIFO before the core can start 348 transmission for the corresponding USB transaction (burst). 349 This count is valid in both host and device modes. It is only used 350 for SuperSpeed operation. 351 Valid values are from 1 to 15. (DWC3 SuperSpeed USB 3.0 Controller 352 Databook) 353 $ref: /schemas/types.yaml#/definitions/uint8 354 minimum: 1 355 maximum: 15 356 357 snps,tx-max-burst: 358 description: 359 Max USB TX burst size. When the system bus is slower than the USB, 360 TX FIFO can underrun during a long burst. Program a smaller value 361 to this field to limit the TX burst size that the core can execute. 362 In Host mode, it only applies to SS Bulk, Isochronous, and Interrupt 363 OUT endpoints. This value is not used in device mode. 364 Valid values are from 1 to 16. (DWC3 SuperSpeed USB 3.0 Controller 365 Databook) 366 $ref: /schemas/types.yaml#/definitions/uint8 367 minimum: 1 368 maximum: 16 369 370 snps,rx-thr-num-pkt-prd: 371 description: 372 Periodic ESS RX packet threshold count (host mode only). Set this and 373 snps,rx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31 374 programming guide section 1.2.4) to enable periodic ESS RX threshold. 375 $ref: /schemas/types.yaml#/definitions/uint8 376 minimum: 1 377 maximum: 16 378 379 snps,rx-max-burst-prd: 380 description: 381 Max periodic ESS RX burst size (host mode only). Set this and 382 snps,rx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31 383 programming guide section 1.2.4) to enable periodic ESS RX threshold. 384 $ref: /schemas/types.yaml#/definitions/uint8 385 minimum: 1 386 maximum: 16 387 388 snps,tx-thr-num-pkt-prd: 389 description: 390 Periodic ESS TX packet threshold count (host mode only). Set this and 391 snps,tx-max-burst-prd to a valid, non-zero value 1-16 (DWC_usb31 392 programming guide section 1.2.3) to enable periodic ESS TX threshold. 393 $ref: /schemas/types.yaml#/definitions/uint8 394 minimum: 1 395 maximum: 16 396 397 snps,tx-max-burst-prd: 398 description: 399 Max periodic ESS TX burst size (host mode only). Set this and 400 snps,tx-thr-num-pkt-prd to a valid, non-zero value 1-16 (DWC_usb31 401 programming guide section 1.2.3) to enable periodic ESS TX threshold. 402 $ref: /schemas/types.yaml#/definitions/uint8 403 minimum: 1 404 maximum: 16 405 406 tx-fifo-resize: 407 description: Determines if the TX fifos can be dynamically resized depending 408 on the number of IN endpoints used and if bursting is supported. This 409 may help improve bandwidth on platforms with higher system latencies, as 410 increased fifo space allows for the controller to prefetch data into its 411 internal memory. 412 type: boolean 413 414 tx-fifo-max-num: 415 description: Specifies the max number of packets the txfifo resizing logic 416 can account for when higher endpoint bursting is used. (bMaxBurst > 6) The 417 higher the number, the more fifo space the txfifo resizing logic will 418 allocate for that endpoint. 419 $ref: /schemas/types.yaml#/definitions/uint8 420 minimum: 3 421 422 snps,incr-burst-type-adjustment: 423 description: 424 Value for INCR burst type of GSBUSCFG0 register, undefined length INCR 425 burst type enable and INCRx type. A single value means INCRX burst mode 426 enabled. If more than one value specified, undefined length INCR burst 427 type will be enabled with burst lengths utilized up to the maximum 428 of the values passed in this property. 429 $ref: /schemas/types.yaml#/definitions/uint32-array 430 minItems: 1 431 maxItems: 8 432 uniqueItems: true 433 items: 434 enum: [1, 4, 8, 16, 32, 64, 128, 256] 435 436 num-hc-interrupters: 437 maximum: 8 438 default: 1 439 440 port: 441 $ref: /schemas/graph.yaml#/properties/port 442 description: 443 This port is used with the 'usb-role-switch' property to connect the 444 dwc3 to type C connector. 445 446 ports: 447 $ref: /schemas/graph.yaml#/properties/ports 448 description: 449 Those ports should be used with any connector to the data bus of this 450 controller using the OF graph bindings specified if the "usb-role-switch" 451 property is used. 452 453 properties: 454 port@0: 455 $ref: /schemas/graph.yaml#/properties/port 456 description: High Speed (HS) data bus. 457 458 port@1: 459 $ref: /schemas/graph.yaml#/properties/port 460 description: Super Speed (SS) data bus. 461 462 wakeup-source: 463 $ref: /schemas/types.yaml#/definitions/flag 464 description: 465 Enable USB remote wakeup. 466 467unevaluatedProperties: false 468 469required: 470 - compatible 471 - reg 472 - interrupts 473 474examples: 475 - | 476 usb@4a030000 { 477 compatible = "snps,dwc3"; 478 reg = <0x4a030000 0xcfff>; 479 interrupts = <0 92 4>; 480 usb-phy = <&usb2_phy>, <&usb3_phy>; 481 snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; 482 }; 483 - | 484 usb@4a000000 { 485 compatible = "snps,dwc3"; 486 reg = <0x4a000000 0xcfff>; 487 interrupts = <0 92 4>; 488 clocks = <&clk 1>, <&clk 2>, <&clk 3>; 489 clock-names = "bus_early", "ref", "suspend"; 490 phys = <&usb2_phy>, <&usb3_phy>; 491 phy-names = "usb2-phy", "usb3-phy"; 492 snps,dis_u2_susphy_quirk; 493 snps,dis_enblslpm_quirk; 494 }; 495... 496