1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Wesley Cheng <quic_wcheng@quicinc.com> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - qcom,ipq4019-dwc3 17 - qcom,ipq5018-dwc3 18 - qcom,ipq5332-dwc3 19 - qcom,ipq6018-dwc3 20 - qcom,ipq8064-dwc3 21 - qcom,ipq8074-dwc3 22 - qcom,ipq9574-dwc3 23 - qcom,msm8953-dwc3 24 - qcom,msm8994-dwc3 25 - qcom,msm8996-dwc3 26 - qcom,msm8998-dwc3 27 - qcom,qcm2290-dwc3 28 - qcom,qcs404-dwc3 29 - qcom,qdu1000-dwc3 30 - qcom,sa8775p-dwc3 31 - qcom,sc7180-dwc3 32 - qcom,sc7280-dwc3 33 - qcom,sc8280xp-dwc3 34 - qcom,sc8280xp-dwc3-mp 35 - qcom,sdm660-dwc3 36 - qcom,sdm670-dwc3 37 - qcom,sdm845-dwc3 38 - qcom,sdx55-dwc3 39 - qcom,sdx65-dwc3 40 - qcom,sdx75-dwc3 41 - qcom,sm4250-dwc3 42 - qcom,sm6115-dwc3 43 - qcom,sm6125-dwc3 44 - qcom,sm6350-dwc3 45 - qcom,sm6375-dwc3 46 - qcom,sm8150-dwc3 47 - qcom,sm8250-dwc3 48 - qcom,sm8350-dwc3 49 - qcom,sm8450-dwc3 50 - qcom,sm8550-dwc3 51 - qcom,sm8650-dwc3 52 - qcom,x1e80100-dwc3 53 - const: qcom,dwc3 54 55 reg: 56 description: Offset and length of register set for QSCRATCH wrapper 57 maxItems: 1 58 59 "#address-cells": 60 enum: [ 1, 2 ] 61 62 "#size-cells": 63 enum: [ 1, 2 ] 64 65 ranges: true 66 67 power-domains: 68 description: specifies a phandle to PM domain provider node 69 maxItems: 1 70 71 required-opps: 72 maxItems: 1 73 74 clocks: 75 description: | 76 Several clocks are used, depending on the variant. Typical ones are:: 77 - cfg_noc:: System Config NOC clock. 78 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 79 60MHz for HS operation. 80 - iface:: System bus AXI clock. 81 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low 82 power mode (U3). 83 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host 84 mode. Its frequency should be 19.2MHz. 85 minItems: 1 86 maxItems: 9 87 88 clock-names: 89 minItems: 1 90 maxItems: 9 91 92 resets: 93 maxItems: 1 94 95 interconnects: 96 maxItems: 2 97 98 interconnect-names: 99 items: 100 - const: usb-ddr 101 - const: apps-usb 102 103 interrupts: 104 description: | 105 Different types of interrupts are used based on HS PHY used on target: 106 - pwr_event: Used for wakeup based on other power events. 107 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is 108 hs_phy_irq which is not triggered by default and its 109 functionality is mutually exclusive to that of 110 {dp/dm}_hs_phy_irq and qusb2_phy_irq. 111 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and 112 expose only a single IRQ whose behavior can be modified 113 by the QUSB2PHY_INTR_CTRL register. The required DPSE/ 114 DMSE configuration is done in QUSB2PHY_INTR_CTRL register 115 of PHY address space. 116 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/ 117 DM pads of the SoC. These are used for wakeup 118 only on SoCs with non-QUSB2 targets with 119 exception of SDM670/SDM845/SM6350. 120 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation. 121 minItems: 2 122 maxItems: 18 123 124 interrupt-names: 125 minItems: 2 126 maxItems: 18 127 128 qcom,select-utmi-as-pipe-clk: 129 description: 130 If present, disable USB3 pipe_clk requirement. 131 Used when dwc3 operates without SSPHY and only 132 HS/FS/LS modes are supported. 133 type: boolean 134 135 wakeup-source: true 136 137# Required child node: 138 139patternProperties: 140 "^usb@[0-9a-f]+$": 141 $ref: snps,dwc3.yaml# 142 unevaluatedProperties: false 143 144 properties: 145 wakeup-source: false 146 147required: 148 - compatible 149 - reg 150 - "#address-cells" 151 - "#size-cells" 152 - ranges 153 - clocks 154 - clock-names 155 - interrupts 156 - interrupt-names 157 158allOf: 159 - if: 160 properties: 161 compatible: 162 contains: 163 enum: 164 - qcom,ipq4019-dwc3 165 then: 166 properties: 167 clocks: 168 maxItems: 3 169 clock-names: 170 items: 171 - const: core 172 - const: sleep 173 - const: mock_utmi 174 175 - if: 176 properties: 177 compatible: 178 contains: 179 enum: 180 - qcom,ipq8064-dwc3 181 then: 182 properties: 183 clocks: 184 items: 185 - description: Master/Core clock, has to be >= 125 MHz 186 for SS operation and >= 60MHz for HS operation. 187 clock-names: 188 items: 189 - const: core 190 191 - if: 192 properties: 193 compatible: 194 contains: 195 enum: 196 - qcom,ipq9574-dwc3 197 - qcom,msm8953-dwc3 198 - qcom,msm8996-dwc3 199 - qcom,msm8998-dwc3 200 - qcom,sa8775p-dwc3 201 - qcom,sc7180-dwc3 202 - qcom,sc7280-dwc3 203 - qcom,sdm670-dwc3 204 - qcom,sdm845-dwc3 205 - qcom,sdx55-dwc3 206 - qcom,sdx65-dwc3 207 - qcom,sdx75-dwc3 208 - qcom,sm6350-dwc3 209 then: 210 properties: 211 clocks: 212 maxItems: 5 213 clock-names: 214 items: 215 - const: cfg_noc 216 - const: core 217 - const: iface 218 - const: sleep 219 - const: mock_utmi 220 221 - if: 222 properties: 223 compatible: 224 contains: 225 enum: 226 - qcom,ipq6018-dwc3 227 then: 228 properties: 229 clocks: 230 minItems: 3 231 maxItems: 4 232 clock-names: 233 oneOf: 234 - items: 235 - const: core 236 - const: sleep 237 - const: mock_utmi 238 - items: 239 - const: cfg_noc 240 - const: core 241 - const: sleep 242 - const: mock_utmi 243 244 - if: 245 properties: 246 compatible: 247 contains: 248 enum: 249 - qcom,ipq8074-dwc3 250 - qcom,qdu1000-dwc3 251 then: 252 properties: 253 clocks: 254 maxItems: 4 255 clock-names: 256 items: 257 - const: cfg_noc 258 - const: core 259 - const: sleep 260 - const: mock_utmi 261 262 - if: 263 properties: 264 compatible: 265 contains: 266 enum: 267 - qcom,ipq5018-dwc3 268 - qcom,ipq5332-dwc3 269 - qcom,msm8994-dwc3 270 - qcom,qcs404-dwc3 271 then: 272 properties: 273 clocks: 274 maxItems: 4 275 clock-names: 276 items: 277 - const: core 278 - const: iface 279 - const: sleep 280 - const: mock_utmi 281 282 - if: 283 properties: 284 compatible: 285 contains: 286 enum: 287 - qcom,sc8280xp-dwc3 288 - qcom,sc8280xp-dwc3-mp 289 - qcom,x1e80100-dwc3 290 then: 291 properties: 292 clocks: 293 maxItems: 9 294 clock-names: 295 items: 296 - const: cfg_noc 297 - const: core 298 - const: iface 299 - const: sleep 300 - const: mock_utmi 301 - const: noc_aggr 302 - const: noc_aggr_north 303 - const: noc_aggr_south 304 - const: noc_sys 305 306 - if: 307 properties: 308 compatible: 309 contains: 310 enum: 311 - qcom,sdm660-dwc3 312 then: 313 properties: 314 clocks: 315 minItems: 4 316 maxItems: 5 317 clock-names: 318 oneOf: 319 - items: 320 - const: cfg_noc 321 - const: core 322 - const: iface 323 - const: sleep 324 - const: mock_utmi 325 - items: 326 - const: cfg_noc 327 - const: core 328 - const: sleep 329 - const: mock_utmi 330 331 - if: 332 properties: 333 compatible: 334 contains: 335 enum: 336 - qcom,qcm2290-dwc3 337 - qcom,sm6115-dwc3 338 - qcom,sm6125-dwc3 339 - qcom,sm8150-dwc3 340 - qcom,sm8250-dwc3 341 - qcom,sm8450-dwc3 342 - qcom,sm8550-dwc3 343 - qcom,sm8650-dwc3 344 then: 345 properties: 346 clocks: 347 minItems: 6 348 clock-names: 349 items: 350 - const: cfg_noc 351 - const: core 352 - const: iface 353 - const: sleep 354 - const: mock_utmi 355 - const: xo 356 357 - if: 358 properties: 359 compatible: 360 contains: 361 enum: 362 - qcom,sm8350-dwc3 363 then: 364 properties: 365 clocks: 366 minItems: 5 367 maxItems: 6 368 clock-names: 369 minItems: 5 370 items: 371 - const: cfg_noc 372 - const: core 373 - const: iface 374 - const: sleep 375 - const: mock_utmi 376 - const: xo 377 378 - if: 379 properties: 380 compatible: 381 contains: 382 enum: 383 - qcom,ipq5018-dwc3 384 - qcom,ipq6018-dwc3 385 - qcom,ipq8074-dwc3 386 - qcom,msm8953-dwc3 387 - qcom,msm8998-dwc3 388 then: 389 properties: 390 interrupts: 391 minItems: 2 392 maxItems: 3 393 interrupt-names: 394 items: 395 - const: pwr_event 396 - const: qusb2_phy 397 - const: ss_phy_irq 398 399 - if: 400 properties: 401 compatible: 402 contains: 403 enum: 404 - qcom,msm8996-dwc3 405 - qcom,qcs404-dwc3 406 - qcom,sdm660-dwc3 407 - qcom,sm6115-dwc3 408 - qcom,sm6125-dwc3 409 then: 410 properties: 411 interrupts: 412 minItems: 3 413 maxItems: 4 414 interrupt-names: 415 items: 416 - const: pwr_event 417 - const: qusb2_phy 418 - const: hs_phy_irq 419 - const: ss_phy_irq 420 421 - if: 422 properties: 423 compatible: 424 contains: 425 enum: 426 - qcom,ipq5332-dwc3 427 - qcom,x1e80100-dwc3 428 then: 429 properties: 430 interrupts: 431 maxItems: 4 432 interrupt-names: 433 items: 434 - const: pwr_event 435 - const: dp_hs_phy_irq 436 - const: dm_hs_phy_irq 437 - const: ss_phy_irq 438 439 - if: 440 properties: 441 compatible: 442 contains: 443 enum: 444 - qcom,ipq4019-dwc3 445 - qcom,ipq8064-dwc3 446 - qcom,msm8994-dwc3 447 - qcom,qdu1000-dwc3 448 - qcom,sa8775p-dwc3 449 - qcom,sc7180-dwc3 450 - qcom,sc7280-dwc3 451 - qcom,sc8280xp-dwc3 452 - qcom,sdm670-dwc3 453 - qcom,sdm845-dwc3 454 - qcom,sdx55-dwc3 455 - qcom,sdx65-dwc3 456 - qcom,sdx75-dwc3 457 - qcom,sm4250-dwc3 458 - qcom,sm6350-dwc3 459 - qcom,sm8150-dwc3 460 - qcom,sm8250-dwc3 461 - qcom,sm8350-dwc3 462 - qcom,sm8450-dwc3 463 - qcom,sm8550-dwc3 464 - qcom,sm8650-dwc3 465 then: 466 properties: 467 interrupts: 468 minItems: 4 469 maxItems: 5 470 interrupt-names: 471 items: 472 - const: pwr_event 473 - const: hs_phy_irq 474 - const: dp_hs_phy_irq 475 - const: dm_hs_phy_irq 476 - const: ss_phy_irq 477 478 - if: 479 properties: 480 compatible: 481 contains: 482 enum: 483 - qcom,sc8280xp-dwc3-mp 484 then: 485 properties: 486 interrupts: 487 minItems: 18 488 maxItems: 18 489 interrupt-names: 490 items: 491 - const: pwr_event_1 492 - const: pwr_event_2 493 - const: pwr_event_3 494 - const: pwr_event_4 495 - const: hs_phy_1 496 - const: hs_phy_2 497 - const: hs_phy_3 498 - const: hs_phy_4 499 - const: dp_hs_phy_1 500 - const: dm_hs_phy_1 501 - const: dp_hs_phy_2 502 - const: dm_hs_phy_2 503 - const: dp_hs_phy_3 504 - const: dm_hs_phy_3 505 - const: dp_hs_phy_4 506 - const: dm_hs_phy_4 507 - const: ss_phy_1 508 - const: ss_phy_2 509 510additionalProperties: false 511 512examples: 513 - | 514 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 515 #include <dt-bindings/interrupt-controller/arm-gic.h> 516 #include <dt-bindings/interrupt-controller/irq.h> 517 soc { 518 #address-cells = <2>; 519 #size-cells = <2>; 520 521 usb@a6f8800 { 522 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 523 reg = <0 0x0a6f8800 0 0x400>; 524 525 #address-cells = <2>; 526 #size-cells = <2>; 527 ranges; 528 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 529 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 530 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 531 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 532 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 533 clock-names = "cfg_noc", 534 "core", 535 "iface", 536 "sleep", 537 "mock_utmi"; 538 539 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 540 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 541 assigned-clock-rates = <19200000>, <150000000>; 542 543 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>, 546 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>, 547 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; 548 interrupt-names = "pwr_event", "hs_phy_irq", 549 "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; 550 551 power-domains = <&gcc USB30_PRIM_GDSC>; 552 553 resets = <&gcc GCC_USB30_PRIM_BCR>; 554 555 usb@a600000 { 556 compatible = "snps,dwc3"; 557 reg = <0 0x0a600000 0 0xcd00>; 558 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 559 iommus = <&apps_smmu 0x740 0>; 560 snps,dis_u2_susphy_quirk; 561 snps,dis_enblslpm_quirk; 562 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 563 phy-names = "usb2-phy", "usb3-phy"; 564 }; 565 }; 566 }; 567