1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Wesley Cheng <quic_wcheng@quicinc.com> 11 12properties: 13 compatible: 14 items: 15 - enum: 16 - qcom,ipq4019-dwc3 17 - qcom,ipq5018-dwc3 18 - qcom,ipq5332-dwc3 19 - qcom,ipq6018-dwc3 20 - qcom,ipq8064-dwc3 21 - qcom,ipq8074-dwc3 22 - qcom,ipq9574-dwc3 23 - qcom,msm8953-dwc3 24 - qcom,msm8994-dwc3 25 - qcom,msm8996-dwc3 26 - qcom,msm8998-dwc3 27 - qcom,qcm2290-dwc3 28 - qcom,qcs404-dwc3 29 - qcom,qcs8300-dwc3 30 - qcom,qdu1000-dwc3 31 - qcom,sa8775p-dwc3 32 - qcom,sar2130p-dwc3 33 - qcom,sc7180-dwc3 34 - qcom,sc7280-dwc3 35 - qcom,sc8180x-dwc3 36 - qcom,sc8180x-dwc3-mp 37 - qcom,sc8280xp-dwc3 38 - qcom,sc8280xp-dwc3-mp 39 - qcom,sdm660-dwc3 40 - qcom,sdm670-dwc3 41 - qcom,sdm845-dwc3 42 - qcom,sdx55-dwc3 43 - qcom,sdx65-dwc3 44 - qcom,sdx75-dwc3 45 - qcom,sm4250-dwc3 46 - qcom,sm6115-dwc3 47 - qcom,sm6125-dwc3 48 - qcom,sm6350-dwc3 49 - qcom,sm6375-dwc3 50 - qcom,sm8150-dwc3 51 - qcom,sm8250-dwc3 52 - qcom,sm8350-dwc3 53 - qcom,sm8450-dwc3 54 - qcom,sm8550-dwc3 55 - qcom,sm8650-dwc3 56 - qcom,x1e80100-dwc3 57 - qcom,x1e80100-dwc3-mp 58 - const: qcom,dwc3 59 60 reg: 61 description: Offset and length of register set for QSCRATCH wrapper 62 maxItems: 1 63 64 "#address-cells": 65 enum: [ 1, 2 ] 66 67 "#size-cells": 68 enum: [ 1, 2 ] 69 70 ranges: true 71 72 power-domains: 73 description: specifies a phandle to PM domain provider node 74 maxItems: 1 75 76 required-opps: 77 maxItems: 1 78 79 clocks: 80 description: | 81 Several clocks are used, depending on the variant. Typical ones are:: 82 - cfg_noc:: System Config NOC clock. 83 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 84 60MHz for HS operation. 85 - iface:: System bus AXI clock. 86 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low 87 power mode (U3). 88 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host 89 mode. Its frequency should be 19.2MHz. 90 minItems: 1 91 maxItems: 9 92 93 clock-names: 94 minItems: 1 95 maxItems: 9 96 97 resets: 98 maxItems: 1 99 100 interconnects: 101 maxItems: 2 102 103 interconnect-names: 104 items: 105 - const: usb-ddr 106 - const: apps-usb 107 108 interrupts: 109 description: | 110 Different types of interrupts are used based on HS PHY used on target: 111 - pwr_event: Used for wakeup based on other power events. 112 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is 113 hs_phy_irq which is not triggered by default and its 114 functionality is mutually exclusive to that of 115 {dp/dm}_hs_phy_irq and qusb2_phy_irq. 116 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and 117 expose only a single IRQ whose behavior can be modified 118 by the QUSB2PHY_INTR_CTRL register. The required DPSE/ 119 DMSE configuration is done in QUSB2PHY_INTR_CTRL register 120 of PHY address space. 121 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/ 122 DM pads of the SoC. These are used for wakeup 123 only on SoCs with non-QUSB2 targets with 124 exception of SDM670/SDM845/SM6350. 125 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation. 126 minItems: 2 127 maxItems: 18 128 129 interrupt-names: 130 minItems: 2 131 maxItems: 18 132 133 qcom,select-utmi-as-pipe-clk: 134 description: 135 If present, disable USB3 pipe_clk requirement. 136 Used when dwc3 operates without SSPHY and only 137 HS/FS/LS modes are supported. 138 type: boolean 139 140 wakeup-source: true 141 142# Required child node: 143 144patternProperties: 145 "^usb@[0-9a-f]+$": 146 $ref: snps,dwc3.yaml# 147 unevaluatedProperties: false 148 149 properties: 150 wakeup-source: false 151 152required: 153 - compatible 154 - reg 155 - "#address-cells" 156 - "#size-cells" 157 - ranges 158 - clocks 159 - clock-names 160 - interrupts 161 - interrupt-names 162 163allOf: 164 - if: 165 properties: 166 compatible: 167 contains: 168 enum: 169 - qcom,ipq4019-dwc3 170 - qcom,ipq5332-dwc3 171 then: 172 properties: 173 clocks: 174 maxItems: 3 175 clock-names: 176 items: 177 - const: core 178 - const: sleep 179 - const: mock_utmi 180 181 - if: 182 properties: 183 compatible: 184 contains: 185 enum: 186 - qcom,ipq8064-dwc3 187 then: 188 properties: 189 clocks: 190 items: 191 - description: Master/Core clock, has to be >= 125 MHz 192 for SS operation and >= 60MHz for HS operation. 193 clock-names: 194 items: 195 - const: core 196 197 - if: 198 properties: 199 compatible: 200 contains: 201 enum: 202 - qcom,ipq9574-dwc3 203 - qcom,msm8953-dwc3 204 - qcom,msm8996-dwc3 205 - qcom,msm8998-dwc3 206 - qcom,qcs8300-dwc3 207 - qcom,sa8775p-dwc3 208 - qcom,sc7180-dwc3 209 - qcom,sc7280-dwc3 210 - qcom,sdm670-dwc3 211 - qcom,sdm845-dwc3 212 - qcom,sdx55-dwc3 213 - qcom,sdx65-dwc3 214 - qcom,sdx75-dwc3 215 - qcom,sm6350-dwc3 216 then: 217 properties: 218 clocks: 219 maxItems: 5 220 clock-names: 221 items: 222 - const: cfg_noc 223 - const: core 224 - const: iface 225 - const: sleep 226 - const: mock_utmi 227 228 - if: 229 properties: 230 compatible: 231 contains: 232 enum: 233 - qcom,ipq6018-dwc3 234 then: 235 properties: 236 clocks: 237 minItems: 3 238 maxItems: 4 239 clock-names: 240 oneOf: 241 - items: 242 - const: core 243 - const: sleep 244 - const: mock_utmi 245 - items: 246 - const: cfg_noc 247 - const: core 248 - const: sleep 249 - const: mock_utmi 250 251 - if: 252 properties: 253 compatible: 254 contains: 255 enum: 256 - qcom,ipq8074-dwc3 257 - qcom,qdu1000-dwc3 258 then: 259 properties: 260 clocks: 261 maxItems: 4 262 clock-names: 263 items: 264 - const: cfg_noc 265 - const: core 266 - const: sleep 267 - const: mock_utmi 268 269 - if: 270 properties: 271 compatible: 272 contains: 273 enum: 274 - qcom,ipq5018-dwc3 275 - qcom,msm8994-dwc3 276 - qcom,qcs404-dwc3 277 then: 278 properties: 279 clocks: 280 maxItems: 4 281 clock-names: 282 items: 283 - const: core 284 - const: iface 285 - const: sleep 286 - const: mock_utmi 287 288 - if: 289 properties: 290 compatible: 291 contains: 292 enum: 293 - qcom,sc8280xp-dwc3 294 - qcom,sc8280xp-dwc3-mp 295 - qcom,x1e80100-dwc3 296 - qcom,x1e80100-dwc3-mp 297 then: 298 properties: 299 clocks: 300 maxItems: 9 301 clock-names: 302 items: 303 - const: cfg_noc 304 - const: core 305 - const: iface 306 - const: sleep 307 - const: mock_utmi 308 - const: noc_aggr 309 - const: noc_aggr_north 310 - const: noc_aggr_south 311 - const: noc_sys 312 313 - if: 314 properties: 315 compatible: 316 contains: 317 enum: 318 - qcom,sdm660-dwc3 319 then: 320 properties: 321 clocks: 322 minItems: 4 323 maxItems: 5 324 clock-names: 325 oneOf: 326 - items: 327 - const: cfg_noc 328 - const: core 329 - const: iface 330 - const: sleep 331 - const: mock_utmi 332 - items: 333 - const: cfg_noc 334 - const: core 335 - const: sleep 336 - const: mock_utmi 337 338 - if: 339 properties: 340 compatible: 341 contains: 342 enum: 343 - qcom,qcm2290-dwc3 344 - qcom,sar2130p-dwc3 345 - qcom,sc8180x-dwc3 346 - qcom,sc8180x-dwc3-mp 347 - qcom,sm6115-dwc3 348 - qcom,sm6125-dwc3 349 - qcom,sm8150-dwc3 350 - qcom,sm8250-dwc3 351 - qcom,sm8450-dwc3 352 - qcom,sm8550-dwc3 353 - qcom,sm8650-dwc3 354 then: 355 properties: 356 clocks: 357 minItems: 6 358 clock-names: 359 items: 360 - const: cfg_noc 361 - const: core 362 - const: iface 363 - const: sleep 364 - const: mock_utmi 365 - const: xo 366 367 - if: 368 properties: 369 compatible: 370 contains: 371 enum: 372 - qcom,sm8350-dwc3 373 then: 374 properties: 375 clocks: 376 minItems: 5 377 maxItems: 6 378 clock-names: 379 minItems: 5 380 items: 381 - const: cfg_noc 382 - const: core 383 - const: iface 384 - const: sleep 385 - const: mock_utmi 386 - const: xo 387 388 - if: 389 properties: 390 compatible: 391 contains: 392 enum: 393 - qcom,ipq5018-dwc3 394 - qcom,ipq6018-dwc3 395 - qcom,ipq8074-dwc3 396 - qcom,msm8953-dwc3 397 - qcom,msm8998-dwc3 398 then: 399 properties: 400 interrupts: 401 minItems: 2 402 maxItems: 3 403 interrupt-names: 404 items: 405 - const: pwr_event 406 - const: qusb2_phy 407 - const: ss_phy_irq 408 409 - if: 410 properties: 411 compatible: 412 contains: 413 enum: 414 - qcom,msm8996-dwc3 415 - qcom,qcs404-dwc3 416 - qcom,sdm660-dwc3 417 - qcom,sm6115-dwc3 418 - qcom,sm6125-dwc3 419 then: 420 properties: 421 interrupts: 422 minItems: 3 423 maxItems: 4 424 interrupt-names: 425 items: 426 - const: pwr_event 427 - const: qusb2_phy 428 - const: hs_phy_irq 429 - const: ss_phy_irq 430 431 - if: 432 properties: 433 compatible: 434 contains: 435 enum: 436 - qcom,ipq5332-dwc3 437 then: 438 properties: 439 interrupts: 440 maxItems: 3 441 interrupt-names: 442 items: 443 - const: pwr_event 444 - const: dp_hs_phy_irq 445 - const: dm_hs_phy_irq 446 447 - if: 448 properties: 449 compatible: 450 contains: 451 enum: 452 - qcom,x1e80100-dwc3 453 then: 454 properties: 455 interrupts: 456 maxItems: 4 457 interrupt-names: 458 items: 459 - const: pwr_event 460 - const: dp_hs_phy_irq 461 - const: dm_hs_phy_irq 462 - const: ss_phy_irq 463 464 - if: 465 properties: 466 compatible: 467 contains: 468 enum: 469 - qcom,ipq4019-dwc3 470 - qcom,ipq8064-dwc3 471 - qcom,msm8994-dwc3 472 - qcom,qcs8300-dwc3 473 - qcom,qdu1000-dwc3 474 - qcom,sa8775p-dwc3 475 - qcom,sc7180-dwc3 476 - qcom,sc7280-dwc3 477 - qcom,sc8180x-dwc3 478 - qcom,sc8280xp-dwc3 479 - qcom,sdm670-dwc3 480 - qcom,sdm845-dwc3 481 - qcom,sdx55-dwc3 482 - qcom,sdx65-dwc3 483 - qcom,sdx75-dwc3 484 - qcom,sm4250-dwc3 485 - qcom,sm6350-dwc3 486 - qcom,sm8150-dwc3 487 - qcom,sm8250-dwc3 488 - qcom,sm8350-dwc3 489 - qcom,sm8450-dwc3 490 - qcom,sm8550-dwc3 491 - qcom,sm8650-dwc3 492 then: 493 properties: 494 interrupts: 495 minItems: 4 496 maxItems: 5 497 interrupt-names: 498 minItems: 4 499 items: 500 - const: pwr_event 501 - const: hs_phy_irq 502 - const: dp_hs_phy_irq 503 - const: dm_hs_phy_irq 504 - const: ss_phy_irq 505 506 - if: 507 properties: 508 compatible: 509 contains: 510 enum: 511 - qcom,sc8180x-dwc3-mp 512 - qcom,x1e80100-dwc3-mp 513 then: 514 properties: 515 interrupts: 516 minItems: 10 517 maxItems: 10 518 interrupt-names: 519 items: 520 - const: pwr_event_1 521 - const: pwr_event_2 522 - const: hs_phy_1 523 - const: hs_phy_2 524 - const: dp_hs_phy_1 525 - const: dm_hs_phy_1 526 - const: dp_hs_phy_2 527 - const: dm_hs_phy_2 528 - const: ss_phy_1 529 - const: ss_phy_2 530 531 - if: 532 properties: 533 compatible: 534 contains: 535 enum: 536 - qcom,sc8280xp-dwc3-mp 537 then: 538 properties: 539 interrupts: 540 minItems: 18 541 maxItems: 18 542 interrupt-names: 543 items: 544 - const: pwr_event_1 545 - const: pwr_event_2 546 - const: pwr_event_3 547 - const: pwr_event_4 548 - const: hs_phy_1 549 - const: hs_phy_2 550 - const: hs_phy_3 551 - const: hs_phy_4 552 - const: dp_hs_phy_1 553 - const: dm_hs_phy_1 554 - const: dp_hs_phy_2 555 - const: dm_hs_phy_2 556 - const: dp_hs_phy_3 557 - const: dm_hs_phy_3 558 - const: dp_hs_phy_4 559 - const: dm_hs_phy_4 560 - const: ss_phy_1 561 - const: ss_phy_2 562 563additionalProperties: false 564 565examples: 566 - | 567 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 568 #include <dt-bindings/interrupt-controller/arm-gic.h> 569 #include <dt-bindings/interrupt-controller/irq.h> 570 soc { 571 #address-cells = <2>; 572 #size-cells = <2>; 573 574 usb@a6f8800 { 575 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 576 reg = <0 0x0a6f8800 0 0x400>; 577 578 #address-cells = <2>; 579 #size-cells = <2>; 580 ranges; 581 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 582 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 583 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 584 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 585 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 586 clock-names = "cfg_noc", 587 "core", 588 "iface", 589 "sleep", 590 "mock_utmi"; 591 592 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 593 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 594 assigned-clock-rates = <19200000>, <150000000>; 595 596 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 597 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 598 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>, 599 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>, 600 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; 601 interrupt-names = "pwr_event", "hs_phy_irq", 602 "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; 603 604 power-domains = <&gcc USB30_PRIM_GDSC>; 605 606 resets = <&gcc GCC_USB30_PRIM_BCR>; 607 608 usb@a600000 { 609 compatible = "snps,dwc3"; 610 reg = <0 0x0a600000 0 0xcd00>; 611 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 612 iommus = <&apps_smmu 0x740 0>; 613 snps,dis_u2_susphy_quirk; 614 snps,dis_enblslpm_quirk; 615 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 616 phy-names = "usb2-phy", "usb3-phy"; 617 }; 618 }; 619 }; 620