1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Legacy Qualcomm SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Wesley Cheng <quic_wcheng@quicinc.com> 11 12# Use the combined qcom,snps-dwc3 instead 13deprecated: true 14 15select: 16 properties: 17 compatible: 18 contains: 19 const: qcom,dwc3 20 required: 21 - compatible 22 23properties: 24 compatible: 25 items: 26 - enum: 27 - qcom,ipq4019-dwc3 28 - qcom,ipq5018-dwc3 29 - qcom,ipq5332-dwc3 30 - qcom,ipq5424-dwc3 31 - qcom,ipq6018-dwc3 32 - qcom,ipq8064-dwc3 33 - qcom,ipq8074-dwc3 34 - qcom,ipq9574-dwc3 35 - qcom,msm8953-dwc3 36 - qcom,msm8994-dwc3 37 - qcom,msm8996-dwc3 38 - qcom,msm8998-dwc3 39 - qcom,qcm2290-dwc3 40 - qcom,qcs404-dwc3 41 - qcom,qcs615-dwc3 42 - qcom,qcs8300-dwc3 43 - qcom,qdu1000-dwc3 44 - qcom,sa8775p-dwc3 45 - qcom,sar2130p-dwc3 46 - qcom,sc7180-dwc3 47 - qcom,sc7280-dwc3 48 - qcom,sc8180x-dwc3 49 - qcom,sc8180x-dwc3-mp 50 - qcom,sc8280xp-dwc3 51 - qcom,sc8280xp-dwc3-mp 52 - qcom,sdm660-dwc3 53 - qcom,sdm670-dwc3 54 - qcom,sdm845-dwc3 55 - qcom,sdx55-dwc3 56 - qcom,sdx65-dwc3 57 - qcom,sdx75-dwc3 58 - qcom,sm4250-dwc3 59 - qcom,sm6115-dwc3 60 - qcom,sm6125-dwc3 61 - qcom,sm6350-dwc3 62 - qcom,sm6375-dwc3 63 - qcom,sm8150-dwc3 64 - qcom,sm8250-dwc3 65 - qcom,sm8350-dwc3 66 - qcom,sm8450-dwc3 67 - qcom,sm8550-dwc3 68 - qcom,sm8650-dwc3 69 - qcom,sm8750-dwc3 70 - qcom,x1e80100-dwc3 71 - qcom,x1e80100-dwc3-mp 72 - const: qcom,dwc3 73 74 reg: 75 description: Offset and length of register set for QSCRATCH wrapper 76 maxItems: 1 77 78 "#address-cells": 79 enum: [ 1, 2 ] 80 81 "#size-cells": 82 enum: [ 1, 2 ] 83 84 ranges: true 85 86 power-domains: 87 description: specifies a phandle to PM domain provider node 88 maxItems: 1 89 90 required-opps: 91 maxItems: 1 92 93 clocks: 94 description: | 95 Several clocks are used, depending on the variant. Typical ones are:: 96 - cfg_noc:: System Config NOC clock. 97 - core:: Master/Core clock, has to be >= 125 MHz for SS operation and >= 98 60MHz for HS operation. 99 - iface:: System bus AXI clock. 100 - sleep:: Sleep clock, used for wakeup when USB3 core goes into low 101 power mode (U3). 102 - mock_utmi:: Mock utmi clock needed for ITP/SOF generation in host 103 mode. Its frequency should be 19.2MHz. 104 minItems: 1 105 maxItems: 9 106 107 clock-names: 108 minItems: 1 109 maxItems: 9 110 111 resets: 112 maxItems: 1 113 114 interconnects: 115 maxItems: 2 116 117 interconnect-names: 118 items: 119 - const: usb-ddr 120 - const: apps-usb 121 122 interrupts: 123 description: | 124 Different types of interrupts are used based on HS PHY used on target: 125 - pwr_event: Used for wakeup based on other power events. 126 - hs_phy_irq: Apart from DP/DM/QUSB2 PHY interrupts, there is 127 hs_phy_irq which is not triggered by default and its 128 functionality is mutually exclusive to that of 129 {dp/dm}_hs_phy_irq and qusb2_phy_irq. 130 - qusb2_phy: SoCs with QUSB2 PHY do not have separate DP/DM IRQs and 131 expose only a single IRQ whose behavior can be modified 132 by the QUSB2PHY_INTR_CTRL register. The required DPSE/ 133 DMSE configuration is done in QUSB2PHY_INTR_CTRL register 134 of PHY address space. 135 - {dp/dm}_hs_phy_irq: These IRQ's directly reflect changes on the DP/ 136 DM pads of the SoC. These are used for wakeup 137 only on SoCs with non-QUSB2 targets with 138 exception of SDM670/SDM845/SM6350. 139 - ss_phy_irq: Used for remote wakeup in Super Speed mode of operation. 140 minItems: 2 141 maxItems: 18 142 143 interrupt-names: 144 minItems: 2 145 maxItems: 18 146 147 qcom,select-utmi-as-pipe-clk: 148 description: 149 If present, disable USB3 pipe_clk requirement. 150 Used when dwc3 operates without SSPHY and only 151 HS/FS/LS modes are supported. 152 type: boolean 153 154 wakeup-source: true 155 156# Required child node: 157 158patternProperties: 159 "^usb@[0-9a-f]+$": 160 $ref: snps,dwc3.yaml# 161 unevaluatedProperties: false 162 163 properties: 164 wakeup-source: false 165 166required: 167 - compatible 168 - reg 169 - "#address-cells" 170 - "#size-cells" 171 - ranges 172 - clocks 173 - clock-names 174 - interrupts 175 - interrupt-names 176 177allOf: 178 - if: 179 properties: 180 compatible: 181 contains: 182 enum: 183 - qcom,ipq4019-dwc3 184 - qcom,ipq5332-dwc3 185 then: 186 properties: 187 clocks: 188 maxItems: 3 189 clock-names: 190 items: 191 - const: core 192 - const: sleep 193 - const: mock_utmi 194 195 - if: 196 properties: 197 compatible: 198 contains: 199 enum: 200 - qcom,ipq8064-dwc3 201 then: 202 properties: 203 clocks: 204 items: 205 - description: Master/Core clock, has to be >= 125 MHz 206 for SS operation and >= 60MHz for HS operation. 207 clock-names: 208 items: 209 - const: core 210 211 - if: 212 properties: 213 compatible: 214 contains: 215 enum: 216 - qcom,ipq9574-dwc3 217 - qcom,msm8953-dwc3 218 - qcom,msm8996-dwc3 219 - qcom,msm8998-dwc3 220 - qcom,qcs8300-dwc3 221 - qcom,sa8775p-dwc3 222 - qcom,sc7180-dwc3 223 - qcom,sc7280-dwc3 224 - qcom,sdm670-dwc3 225 - qcom,sdm845-dwc3 226 - qcom,sdx55-dwc3 227 - qcom,sdx65-dwc3 228 - qcom,sdx75-dwc3 229 - qcom,sm6350-dwc3 230 then: 231 properties: 232 clocks: 233 maxItems: 5 234 clock-names: 235 items: 236 - const: cfg_noc 237 - const: core 238 - const: iface 239 - const: sleep 240 - const: mock_utmi 241 242 - if: 243 properties: 244 compatible: 245 contains: 246 enum: 247 - qcom,ipq6018-dwc3 248 then: 249 properties: 250 clocks: 251 minItems: 3 252 maxItems: 4 253 clock-names: 254 oneOf: 255 - items: 256 - const: core 257 - const: sleep 258 - const: mock_utmi 259 - items: 260 - const: cfg_noc 261 - const: core 262 - const: sleep 263 - const: mock_utmi 264 265 - if: 266 properties: 267 compatible: 268 contains: 269 enum: 270 - qcom,ipq8074-dwc3 271 - qcom,qdu1000-dwc3 272 then: 273 properties: 274 clocks: 275 maxItems: 4 276 clock-names: 277 items: 278 - const: cfg_noc 279 - const: core 280 - const: sleep 281 - const: mock_utmi 282 283 - if: 284 properties: 285 compatible: 286 contains: 287 enum: 288 - qcom,ipq5018-dwc3 289 - qcom,msm8994-dwc3 290 - qcom,qcs404-dwc3 291 then: 292 properties: 293 clocks: 294 maxItems: 4 295 clock-names: 296 items: 297 - const: core 298 - const: iface 299 - const: sleep 300 - const: mock_utmi 301 302 - if: 303 properties: 304 compatible: 305 contains: 306 enum: 307 - qcom,sc8280xp-dwc3 308 - qcom,sc8280xp-dwc3-mp 309 - qcom,x1e80100-dwc3 310 - qcom,x1e80100-dwc3-mp 311 then: 312 properties: 313 clocks: 314 maxItems: 9 315 clock-names: 316 items: 317 - const: cfg_noc 318 - const: core 319 - const: iface 320 - const: sleep 321 - const: mock_utmi 322 - const: noc_aggr 323 - const: noc_aggr_north 324 - const: noc_aggr_south 325 - const: noc_sys 326 327 - if: 328 properties: 329 compatible: 330 contains: 331 enum: 332 - qcom,sdm660-dwc3 333 then: 334 properties: 335 clocks: 336 minItems: 4 337 maxItems: 5 338 clock-names: 339 oneOf: 340 - items: 341 - const: cfg_noc 342 - const: core 343 - const: iface 344 - const: sleep 345 - const: mock_utmi 346 - items: 347 - const: cfg_noc 348 - const: core 349 - const: sleep 350 - const: mock_utmi 351 352 - if: 353 properties: 354 compatible: 355 contains: 356 enum: 357 - qcom,qcm2290-dwc3 358 - qcom,qcs615-dwc3 359 - qcom,sar2130p-dwc3 360 - qcom,sc8180x-dwc3 361 - qcom,sc8180x-dwc3-mp 362 - qcom,sm6115-dwc3 363 - qcom,sm6125-dwc3 364 - qcom,sm8150-dwc3 365 - qcom,sm8250-dwc3 366 - qcom,sm8450-dwc3 367 - qcom,sm8550-dwc3 368 - qcom,sm8650-dwc3 369 - qcom,sm8750-dwc3 370 then: 371 properties: 372 clocks: 373 minItems: 6 374 clock-names: 375 items: 376 - const: cfg_noc 377 - const: core 378 - const: iface 379 - const: sleep 380 - const: mock_utmi 381 - const: xo 382 383 - if: 384 properties: 385 compatible: 386 contains: 387 enum: 388 - qcom,sm8350-dwc3 389 then: 390 properties: 391 clocks: 392 minItems: 5 393 maxItems: 6 394 clock-names: 395 minItems: 5 396 items: 397 - const: cfg_noc 398 - const: core 399 - const: iface 400 - const: sleep 401 - const: mock_utmi 402 - const: xo 403 404 - if: 405 properties: 406 compatible: 407 contains: 408 enum: 409 - qcom,ipq5018-dwc3 410 - qcom,ipq6018-dwc3 411 - qcom,ipq8074-dwc3 412 - qcom,msm8953-dwc3 413 - qcom,msm8998-dwc3 414 then: 415 properties: 416 interrupts: 417 minItems: 2 418 maxItems: 3 419 interrupt-names: 420 minItems: 2 421 items: 422 - const: pwr_event 423 - const: qusb2_phy 424 - const: ss_phy_irq 425 426 - if: 427 properties: 428 compatible: 429 contains: 430 enum: 431 - qcom,msm8996-dwc3 432 - qcom,qcs404-dwc3 433 - qcom,sdm660-dwc3 434 - qcom,sm6115-dwc3 435 - qcom,sm6125-dwc3 436 then: 437 properties: 438 interrupts: 439 minItems: 3 440 maxItems: 4 441 interrupt-names: 442 minItems: 3 443 items: 444 - const: pwr_event 445 - const: qusb2_phy 446 - const: hs_phy_irq 447 - const: ss_phy_irq 448 449 - if: 450 properties: 451 compatible: 452 contains: 453 enum: 454 - qcom,ipq5332-dwc3 455 then: 456 properties: 457 interrupts: 458 maxItems: 3 459 interrupt-names: 460 items: 461 - const: pwr_event 462 - const: dp_hs_phy_irq 463 - const: dm_hs_phy_irq 464 465 - if: 466 properties: 467 compatible: 468 contains: 469 enum: 470 - qcom,x1e80100-dwc3 471 then: 472 properties: 473 interrupts: 474 minItems: 3 475 maxItems: 4 476 interrupt-names: 477 minItems: 3 478 items: 479 - const: pwr_event 480 - const: dp_hs_phy_irq 481 - const: dm_hs_phy_irq 482 - const: ss_phy_irq 483 484 - if: 485 properties: 486 compatible: 487 contains: 488 enum: 489 - qcom,ipq4019-dwc3 490 - qcom,ipq8064-dwc3 491 - qcom,msm8994-dwc3 492 - qcom,qcs615-dwc3 493 - qcom,qcs8300-dwc3 494 - qcom,qdu1000-dwc3 495 - qcom,sa8775p-dwc3 496 - qcom,sc7180-dwc3 497 - qcom,sc7280-dwc3 498 - qcom,sc8180x-dwc3 499 - qcom,sc8280xp-dwc3 500 - qcom,sdm670-dwc3 501 - qcom,sdm845-dwc3 502 - qcom,sdx55-dwc3 503 - qcom,sdx65-dwc3 504 - qcom,sdx75-dwc3 505 - qcom,sm4250-dwc3 506 - qcom,sm6350-dwc3 507 - qcom,sm8150-dwc3 508 - qcom,sm8250-dwc3 509 - qcom,sm8350-dwc3 510 - qcom,sm8450-dwc3 511 - qcom,sm8550-dwc3 512 - qcom,sm8650-dwc3 513 - qcom,sm8750-dwc3 514 then: 515 properties: 516 interrupts: 517 minItems: 4 518 maxItems: 5 519 interrupt-names: 520 minItems: 4 521 items: 522 - const: pwr_event 523 - const: hs_phy_irq 524 - const: dp_hs_phy_irq 525 - const: dm_hs_phy_irq 526 - const: ss_phy_irq 527 528 - if: 529 properties: 530 compatible: 531 contains: 532 enum: 533 - qcom,sc8180x-dwc3-mp 534 - qcom,x1e80100-dwc3-mp 535 then: 536 properties: 537 interrupts: 538 minItems: 10 539 maxItems: 10 540 interrupt-names: 541 items: 542 - const: pwr_event_1 543 - const: pwr_event_2 544 - const: hs_phy_1 545 - const: hs_phy_2 546 - const: dp_hs_phy_1 547 - const: dm_hs_phy_1 548 - const: dp_hs_phy_2 549 - const: dm_hs_phy_2 550 - const: ss_phy_1 551 - const: ss_phy_2 552 553 - if: 554 properties: 555 compatible: 556 contains: 557 enum: 558 - qcom,sc8280xp-dwc3-mp 559 then: 560 properties: 561 interrupts: 562 minItems: 18 563 maxItems: 18 564 interrupt-names: 565 items: 566 - const: pwr_event_1 567 - const: pwr_event_2 568 - const: pwr_event_3 569 - const: pwr_event_4 570 - const: hs_phy_1 571 - const: hs_phy_2 572 - const: hs_phy_3 573 - const: hs_phy_4 574 - const: dp_hs_phy_1 575 - const: dm_hs_phy_1 576 - const: dp_hs_phy_2 577 - const: dm_hs_phy_2 578 - const: dp_hs_phy_3 579 - const: dm_hs_phy_3 580 - const: dp_hs_phy_4 581 - const: dm_hs_phy_4 582 - const: ss_phy_1 583 - const: ss_phy_2 584 585additionalProperties: false 586 587examples: 588 - | 589 #include <dt-bindings/clock/qcom,gcc-sdm845.h> 590 #include <dt-bindings/interrupt-controller/arm-gic.h> 591 #include <dt-bindings/interrupt-controller/irq.h> 592 soc { 593 #address-cells = <2>; 594 #size-cells = <2>; 595 596 usb@a6f8800 { 597 compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; 598 reg = <0 0x0a6f8800 0 0x400>; 599 600 #address-cells = <2>; 601 #size-cells = <2>; 602 ranges; 603 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 604 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 605 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 606 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 607 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 608 clock-names = "cfg_noc", 609 "core", 610 "iface", 611 "sleep", 612 "mock_utmi"; 613 614 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 615 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 616 assigned-clock-rates = <19200000>, <150000000>; 617 618 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 619 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 620 <GIC_SPI 489 IRQ_TYPE_EDGE_BOTH>, 621 <GIC_SPI 488 IRQ_TYPE_EDGE_BOTH>, 622 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; 623 interrupt-names = "pwr_event", "hs_phy_irq", 624 "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; 625 626 power-domains = <&gcc USB30_PRIM_GDSC>; 627 628 resets = <&gcc GCC_USB30_PRIM_BCR>; 629 630 usb@a600000 { 631 compatible = "snps,dwc3"; 632 reg = <0 0x0a600000 0 0xcd00>; 633 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; 634 iommus = <&apps_smmu 0x740 0>; 635 snps,dis_u2_susphy_quirk; 636 snps,dis_enblslpm_quirk; 637 phys = <&usb_1_hsphy>, <&usb_1_ssphy>; 638 phy-names = "usb2-phy", "usb3-phy"; 639 }; 640 }; 641 }; 642