1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/nvidia,tegra234-xusb.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra234 xHCI controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13description: | 14 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by 15 the Tegra XUSB pad controller. The xHCI controller controls up to eight 16 ports; there are four USB 2.0 ports and four USB 3.2 Gen1 x1 ports. 17 18properties: 19 compatible: 20 const: nvidia,tegra234-xusb 21 22 reg: 23 items: 24 - description: xHCI host registers 25 - description: XUSB FPCI registers 26 - description: XUSB bar2 registers 27 28 reg-names: 29 items: 30 - const: hcd 31 - const: fpci 32 - const: bar2 33 34 interrupts: 35 minItems: 2 36 items: 37 - description: xHCI host interrupt 38 - description: mailbox interrupt 39 - description: USB wake event 0 40 - description: USB wake event 1 41 - description: USB wake event 2 42 - description: USB wake event 3 43 - description: USB wake event 4 44 - description: USB wake event 5 45 - description: USB wake event 6 46 description: | 47 The first two interrupts are required for the USB host controller. The 48 remaining USB wake event interrupts are optional. Each USB wake event is 49 independent; it is not necessary to use all of these events on a 50 platform. The USB host controller can function even if no wake-up events 51 are defined. The USB wake event interrupts are handled by the Tegra PMC; 52 hence, the interrupt controller for these is the PMC and the interrupt 53 IDs correspond to the PMC wake event IDs. A complete list of wake event 54 IDs is provided below, and this information is also present in the Tegra 55 TRM document. 56 57 PMC wake-up 76 for USB3 port 0 wakeup 58 PMC wake-up 77 for USB3 port 1 wakeup 59 PMC wake-up 78 for USB3 port 2 and port 3 wakeup 60 PMC wake-up 79 for USB2 port 0 wakeup 61 PMC wake-up 80 for USB2 port 1 wakeup 62 PMC wake-up 81 for USB2 port 2 wakeup 63 PMC wake-up 82 for USB2 port 3 wakeup 64 65 clocks: 66 items: 67 - description: XUSB host clock 68 - description: XUSB Falcon source clock 69 - description: XUSB SuperSpeed clock 70 - description: XUSB SuperSpeed source clock 71 - description: XUSB HighSpeed clock source 72 - description: XUSB FullSpeed clock source 73 - description: USB PLL 74 - description: reference clock 75 - description: I/O PLL 76 77 clock-names: 78 items: 79 - const: xusb_host 80 - const: xusb_falcon_src 81 - const: xusb_ss 82 - const: xusb_ss_src 83 - const: xusb_hs_src 84 - const: xusb_fs_src 85 - const: pll_u_480m 86 - const: clk_m 87 - const: pll_e 88 89 interconnects: 90 items: 91 - description: read client 92 - description: write client 93 94 interconnect-names: 95 items: 96 - const: dma-mem # read 97 - const: write 98 99 iommus: 100 maxItems: 1 101 102 nvidia,xusb-padctl: 103 $ref: /schemas/types.yaml#/definitions/phandle 104 description: phandle to the XUSB pad controller that is used to configure 105 the USB pads used by the XHCI controller 106 107 phys: 108 minItems: 1 109 maxItems: 8 110 111 phy-names: 112 minItems: 1 113 maxItems: 8 114 items: 115 enum: 116 - usb2-0 117 - usb2-1 118 - usb2-2 119 - usb2-3 120 - usb3-0 121 - usb3-1 122 - usb3-2 123 - usb3-3 124 125 power-domains: 126 items: 127 - description: XUSBC power domain (for Host and USB 2.0) 128 - description: XUSBA power domain (for SuperSpeed) 129 130 power-domain-names: 131 items: 132 - const: xusb_host 133 - const: xusb_ss 134 135 dma-coherent: true 136 137allOf: 138 - $ref: usb-xhci.yaml 139 140unevaluatedProperties: false 141 142examples: 143 - | 144 #include <dt-bindings/clock/tegra234-clock.h> 145 #include <dt-bindings/interrupt-controller/arm-gic.h> 146 #include <dt-bindings/memory/tegra234-mc.h> 147 #include <dt-bindings/power/tegra234-powergate.h> 148 149 usb@3610000 { 150 compatible = "nvidia,tegra234-xusb"; 151 reg = <0x03610000 0x40000>, 152 <0x03600000 0x10000>, 153 <0x03650000 0x10000>; 154 reg-names = "hcd", "fpci", "bar2"; 155 156 interrupts-extended = <&gic GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 157 <&gic GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, 158 <&pmc 76 IRQ_TYPE_LEVEL_HIGH>; 159 160 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 161 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 162 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 163 <&bpmp TEGRA234_CLK_XUSB_SS>, 164 <&bpmp TEGRA234_CLK_CLK_M>, 165 <&bpmp TEGRA234_CLK_XUSB_FS>, 166 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 167 <&bpmp TEGRA234_CLK_CLK_M>, 168 <&bpmp TEGRA234_CLK_PLLE>; 169 clock-names = "xusb_host", "xusb_falcon_src", 170 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 171 "xusb_fs_src", "pll_u_480m", "clk_m", 172 "pll_e"; 173 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 174 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 175 interconnect-names = "dma-mem", "write"; 176 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 177 178 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 179 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 180 power-domain-names = "xusb_host", "xusb_ss"; 181 182 nvidia,xusb-padctl = <&xusb_padctl>; 183 184 phys = <&pad_lanes_usb2_0>; 185 phy-names = "usb2-0"; 186 }; 187