1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/nvidia,tegra234-xusb.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: NVIDIA Tegra234 xHCI controller 8 9maintainers: 10 - Thierry Reding <thierry.reding@gmail.com> 11 - Jon Hunter <jonathanh@nvidia.com> 12 13description: | 14 The Tegra xHCI controller supports both USB2 and USB3 interfaces exposed by 15 the Tegra XUSB pad controller. The xHCI controller controls up to eight 16 ports; there are four USB 2.0 ports and four USB 3.2 Gen1 x1 ports. 17 18properties: 19 compatible: 20 const: nvidia,tegra234-xusb 21 22 reg: 23 items: 24 - description: xHCI host registers 25 - description: XUSB FPCI registers 26 - description: XUSB bar2 registers 27 28 reg-names: 29 items: 30 - const: hcd 31 - const: fpci 32 - const: bar2 33 34 interrupts: 35 items: 36 - description: xHCI host interrupt 37 - description: mailbox interrupt 38 39 clocks: 40 items: 41 - description: XUSB host clock 42 - description: XUSB Falcon source clock 43 - description: XUSB SuperSpeed clock 44 - description: XUSB SuperSpeed source clock 45 - description: XUSB HighSpeed clock source 46 - description: XUSB FullSpeed clock source 47 - description: USB PLL 48 - description: reference clock 49 - description: I/O PLL 50 51 clock-names: 52 items: 53 - const: xusb_host 54 - const: xusb_falcon_src 55 - const: xusb_ss 56 - const: xusb_ss_src 57 - const: xusb_hs_src 58 - const: xusb_fs_src 59 - const: pll_u_480m 60 - const: clk_m 61 - const: pll_e 62 63 interconnects: 64 items: 65 - description: read client 66 - description: write client 67 68 interconnect-names: 69 items: 70 - const: dma-mem # read 71 - const: write 72 73 iommus: 74 maxItems: 1 75 76 nvidia,xusb-padctl: 77 $ref: /schemas/types.yaml#/definitions/phandle 78 description: phandle to the XUSB pad controller that is used to configure 79 the USB pads used by the XHCI controller 80 81 phys: 82 minItems: 1 83 maxItems: 8 84 85 phy-names: 86 minItems: 1 87 maxItems: 8 88 items: 89 enum: 90 - usb2-0 91 - usb2-1 92 - usb2-2 93 - usb2-3 94 - usb3-0 95 - usb3-1 96 - usb3-2 97 - usb3-3 98 99 power-domains: 100 items: 101 - description: XUSBC power domain (for Host and USB 2.0) 102 - description: XUSBA power domain (for SuperSpeed) 103 104 power-domain-names: 105 items: 106 - const: xusb_host 107 - const: xusb_ss 108 109 dma-coherent: true 110 111allOf: 112 - $ref: usb-xhci.yaml 113 114unevaluatedProperties: false 115 116examples: 117 - | 118 #include <dt-bindings/clock/tegra234-clock.h> 119 #include <dt-bindings/interrupt-controller/arm-gic.h> 120 #include <dt-bindings/memory/tegra234-mc.h> 121 #include <dt-bindings/power/tegra234-powergate.h> 122 123 usb@3610000 { 124 compatible = "nvidia,tegra234-xusb"; 125 reg = <0x03610000 0x40000>, 126 <0x03600000 0x10000>, 127 <0x03650000 0x10000>; 128 reg-names = "hcd", "fpci", "bar2"; 129 130 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, 131 <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 132 133 clocks = <&bpmp TEGRA234_CLK_XUSB_CORE_HOST>, 134 <&bpmp TEGRA234_CLK_XUSB_FALCON>, 135 <&bpmp TEGRA234_CLK_XUSB_CORE_SS>, 136 <&bpmp TEGRA234_CLK_XUSB_SS>, 137 <&bpmp TEGRA234_CLK_CLK_M>, 138 <&bpmp TEGRA234_CLK_XUSB_FS>, 139 <&bpmp TEGRA234_CLK_UTMIP_PLL>, 140 <&bpmp TEGRA234_CLK_CLK_M>, 141 <&bpmp TEGRA234_CLK_PLLE>; 142 clock-names = "xusb_host", "xusb_falcon_src", 143 "xusb_ss", "xusb_ss_src", "xusb_hs_src", 144 "xusb_fs_src", "pll_u_480m", "clk_m", 145 "pll_e"; 146 interconnects = <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTR &emc>, 147 <&mc TEGRA234_MEMORY_CLIENT_XUSB_HOSTW &emc>; 148 interconnect-names = "dma-mem", "write"; 149 iommus = <&smmu_niso1 TEGRA234_SID_XUSB_HOST>; 150 151 power-domains = <&bpmp TEGRA234_POWER_DOMAIN_XUSBC>, 152 <&bpmp TEGRA234_POWER_DOMAIN_XUSBA>; 153 power-domain-names = "xusb_host", "xusb_ss"; 154 155 nvidia,xusb-padctl = <&xusb_padctl>; 156 157 phys = <&pad_lanes_usb2_0>; 158 phy-names = "usb2-0"; 159 }; 160