xref: /linux/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml (revision 7f71507851fc7764b36a3221839607d3a45c2025) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 NXP
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: NXP iMX8MP Soc USB Controller
9
10maintainers:
11  - Li Jun <jun.li@nxp.com>
12
13properties:
14  compatible:
15    oneOf:
16      - items:
17          - const: fsl,imx95-dwc3
18          - const: fsl,imx8mp-dwc3
19      - const: fsl,imx8mp-dwc3
20
21  reg:
22    items:
23      - description: Address and length of the register set for HSIO Block Control
24      - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.
25
26  "#address-cells":
27    enum: [ 1, 2 ]
28
29  "#size-cells":
30    enum: [ 1, 2 ]
31
32  dma-ranges:
33    description:
34      See section 2.3.9 of the DeviceTree Specification.
35
36  ranges: true
37
38  interrupts:
39    maxItems: 1
40    description: The interrupt that is asserted when a wakeup event is
41      received.
42
43  clocks:
44    description:
45      A list of phandle and clock-specifier pairs for the clocks
46      listed in clock-names.
47    items:
48      - description: system hsio root clock.
49      - description: suspend clock, used for usb wakeup logic.
50
51  clock-names:
52    items:
53      - const: hsio
54      - const: suspend
55
56  fsl,permanently-attached:
57    type: boolean
58    description:
59      Indicates if the device attached to a downstream port is
60      permanently attached.
61
62  fsl,disable-port-power-control:
63    type: boolean
64    description:
65      Indicates whether the host controller implementation includes port
66      power control. Defines Bit 3 in capability register (HCCPARAMS).
67
68  fsl,over-current-active-low:
69    type: boolean
70    description:
71      Over current signal polarity is active low.
72
73  fsl,power-active-low:
74    type: boolean
75    description:
76      Power pad (PWR) polarity is active low.
77
78  power-domains:
79    maxItems: 1
80
81# Required child node:
82
83patternProperties:
84  "^usb@[0-9a-f]+$":
85    $ref: snps,dwc3.yaml#
86
87required:
88  - compatible
89  - reg
90  - "#address-cells"
91  - "#size-cells"
92  - dma-ranges
93  - ranges
94  - clocks
95  - clock-names
96  - interrupts
97  - power-domains
98
99additionalProperties: false
100
101examples:
102  - |
103    #include <dt-bindings/clock/imx8mp-clock.h>
104    #include <dt-bindings/power/imx8mp-power.h>
105    #include <dt-bindings/interrupt-controller/arm-gic.h>
106    usb3_0: usb@32f10100 {
107      compatible = "fsl,imx8mp-dwc3";
108      reg = <0x32f10100 0x8>,
109            <0x381f0000 0x20>;
110      clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
111               <&clk IMX8MP_CLK_USB_ROOT>;
112      clock-names = "hsio", "suspend";
113      interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
114      power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
115      #address-cells = <1>;
116      #size-cells = <1>;
117      dma-ranges = <0x40000000 0x40000000 0xc0000000>;
118      ranges;
119
120      usb@38100000 {
121        compatible = "snps,dwc3";
122        reg = <0x38100000 0x10000>;
123        clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
124                 <&clk IMX8MP_CLK_USB_CORE_REF>,
125                 <&clk IMX8MP_CLK_USB_ROOT>;
126        clock-names = "bus_early", "ref", "suspend";
127        assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
128        assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
129        assigned-clock-rates = <500000000>;
130        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
131        phys = <&usb3_phy0>, <&usb3_phy0>;
132        phy-names = "usb2-phy", "usb3-phy";
133        snps,dis-u2-freeclk-exists-quirk;
134      };
135    };
136