xref: /linux/Documentation/devicetree/bindings/usb/fsl,imx8mp-dwc3.yaml (revision 34dc1baba215b826e454b8d19e4f24adbeb7d00d) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2# Copyright (c) 2020 NXP
3%YAML 1.2
4---
5$id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
6$schema: http://devicetree.org/meta-schemas/core.yaml#
7
8title: NXP iMX8MP Soc USB Controller
9
10maintainers:
11  - Li Jun <jun.li@nxp.com>
12
13properties:
14  compatible:
15    const: fsl,imx8mp-dwc3
16
17  reg:
18    items:
19      - description: Address and length of the register set for HSIO Block Control
20      - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.
21
22  "#address-cells":
23    enum: [ 1, 2 ]
24
25  "#size-cells":
26    enum: [ 1, 2 ]
27
28  dma-ranges:
29    description:
30      See section 2.3.9 of the DeviceTree Specification.
31
32  ranges: true
33
34  interrupts:
35    maxItems: 1
36    description: The interrupt that is asserted when a wakeup event is
37      received.
38
39  clocks:
40    description:
41      A list of phandle and clock-specifier pairs for the clocks
42      listed in clock-names.
43    items:
44      - description: system hsio root clock.
45      - description: suspend clock, used for usb wakeup logic.
46
47  clock-names:
48    items:
49      - const: hsio
50      - const: suspend
51
52  fsl,permanently-attached:
53    type: boolean
54    description:
55      Indicates if the device attached to a downstream port is
56      permanently attached.
57
58  fsl,disable-port-power-control:
59    type: boolean
60    description:
61      Indicates whether the host controller implementation includes port
62      power control. Defines Bit 3 in capability register (HCCPARAMS).
63
64  fsl,over-current-active-low:
65    type: boolean
66    description:
67      Over current signal polarity is active low.
68
69  fsl,power-active-low:
70    type: boolean
71    description:
72      Power pad (PWR) polarity is active low.
73
74  power-domains:
75    maxItems: 1
76
77# Required child node:
78
79patternProperties:
80  "^usb@[0-9a-f]+$":
81    $ref: snps,dwc3.yaml#
82
83required:
84  - compatible
85  - reg
86  - "#address-cells"
87  - "#size-cells"
88  - dma-ranges
89  - ranges
90  - clocks
91  - clock-names
92  - interrupts
93  - power-domains
94
95additionalProperties: false
96
97examples:
98  - |
99    #include <dt-bindings/clock/imx8mp-clock.h>
100    #include <dt-bindings/power/imx8mp-power.h>
101    #include <dt-bindings/interrupt-controller/arm-gic.h>
102    usb3_0: usb@32f10100 {
103      compatible = "fsl,imx8mp-dwc3";
104      reg = <0x32f10100 0x8>,
105            <0x381f0000 0x20>;
106      clocks = <&clk IMX8MP_CLK_HSIO_ROOT>,
107               <&clk IMX8MP_CLK_USB_ROOT>;
108      clock-names = "hsio", "suspend";
109      interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
110      power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
111      #address-cells = <1>;
112      #size-cells = <1>;
113      dma-ranges = <0x40000000 0x40000000 0xc0000000>;
114      ranges;
115
116      usb@38100000 {
117        compatible = "snps,dwc3";
118        reg = <0x38100000 0x10000>;
119        clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
120                 <&clk IMX8MP_CLK_USB_CORE_REF>,
121                 <&clk IMX8MP_CLK_USB_ROOT>;
122        clock-names = "bus_early", "ref", "suspend";
123        assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
124        assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
125        assigned-clock-rates = <500000000>;
126        interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
127        phys = <&usb3_phy0>, <&usb3_phy0>;
128        phy-names = "usb2-phy", "usb3-phy";
129        snps,dis-u2-freeclk-exists-quirk;
130      };
131    };
132