xref: /linux/Documentation/devicetree/bindings/usb/dwc3-xilinx.yaml (revision e7e86d7697c6ed1dbbde18d7185c35b6967945ed) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Xilinx SuperSpeed DWC3 USB SoC controller
8
9maintainers:
10  - Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
11
12properties:
13  compatible:
14    items:
15      - enum:
16          - xlnx,zynqmp-dwc3
17          - xlnx,versal-dwc3
18  reg:
19    maxItems: 1
20
21  "#address-cells":
22    enum: [ 1, 2 ]
23
24  "#size-cells":
25    enum: [ 1, 2 ]
26
27  ranges: true
28
29  dma-coherent: true
30
31  power-domains:
32    description: specifies a phandle to PM domain provider node
33    maxItems: 1
34
35  clocks:
36    description:
37      A list of phandle and clock-specifier pairs for the clocks
38      listed in clock-names.
39    items:
40      - description: Master/Core clock, has to be >= 125 MHz
41          for SS operation and >= 60MHz for HS operation.
42      - description: Clock source to core during PHY power down.
43
44  clock-names:
45    items:
46      - const: bus_clk
47      - const: ref_clk
48
49  resets:
50    description:
51      A list of phandles for resets listed in reset-names.
52
53    items:
54      - description: USB core reset
55      - description: USB hibernation reset
56      - description: USB APB reset
57
58  reset-names:
59    items:
60      - const: usb_crst
61      - const: usb_hibrst
62      - const: usb_apbrst
63
64  phys:
65    minItems: 1
66    maxItems: 2
67
68  phy-names:
69    minItems: 1
70    maxItems: 2
71    items:
72      enum:
73        - usb2-phy
74        - usb3-phy
75
76  reset-gpios:
77    description: GPIO used for the reset ulpi-phy
78    maxItems: 1
79
80# Required child node:
81
82patternProperties:
83  "^usb@[0-9a-f]+$":
84    $ref: snps,dwc3.yaml#
85
86required:
87  - compatible
88  - reg
89  - "#address-cells"
90  - "#size-cells"
91  - ranges
92  - power-domains
93  - clocks
94  - clock-names
95  - resets
96  - reset-names
97
98additionalProperties: false
99
100examples:
101  - |
102    #include <dt-bindings/dma/xlnx-zynqmp-dpdma.h>
103    #include <dt-bindings/power/xlnx-zynqmp-power.h>
104    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
105    #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
106    #include <dt-bindings/phy/phy.h>
107    axi {
108        #address-cells = <2>;
109        #size-cells = <2>;
110
111        usb@0 {
112            #address-cells = <0x2>;
113            #size-cells = <0x2>;
114            compatible = "xlnx,zynqmp-dwc3";
115            reg = <0x0 0xff9d0000 0x0 0x100>;
116            clocks = <&zynqmp_clk 32>, <&zynqmp_clk 34>;
117            clock-names = "bus_clk", "ref_clk";
118            power-domains = <&zynqmp_firmware PD_USB_0>;
119            resets = <&zynqmp_reset ZYNQMP_RESET_USB1_CORERESET>,
120                     <&zynqmp_reset ZYNQMP_RESET_USB1_HIBERRESET>,
121                     <&zynqmp_reset ZYNQMP_RESET_USB1_APB>;
122            reset-names = "usb_crst", "usb_hibrst", "usb_apbrst";
123            phys = <&psgtr 2 PHY_TYPE_USB3 0 2>;
124            phy-names = "usb3-phy";
125            ranges;
126
127            usb@fe200000 {
128                compatible = "snps,dwc3";
129                reg = <0x0 0xfe200000 0x0 0x40000>;
130                interrupt-names = "host", "otg";
131                interrupts = <0 65 4>, <0 69 4>;
132                dr_mode = "host";
133                dma-coherent;
134            };
135        };
136    };
137