1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/usb/aspeed,dwc3.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Aspeed SuperSpeed DWC3 USB SoC controller 8 9maintainers: 10 - Ryan Chen <ryan_chen@aspeedtech.com> 11 12description: 13 The common content of the node is defined in snps,dwc3.yaml. 14 15select: 16 properties: 17 compatible: 18 contains: 19 const: aspeed,ast2700-xhci 20 required: 21 - compatible 22 23properties: 24 compatible: 25 items: 26 - const: aspeed,ast2700-xhci 27 - const: snps,dwc3 28 29 interrupts: 30 maxItems: 1 31 32 clocks: 33 items: 34 - description: Controller bus early clock 35 - description: PHY reference clock 36 - description: Controller suspend clock 37 38 clock-names: 39 items: 40 - const: bus_early 41 - const: ref 42 - const: suspend 43 44 resets: 45 maxItems: 1 46 47 phys: 48 maxItems: 1 49 50 phy-names: 51 const: usb3-phy 52 53required: 54 - compatible 55 - reg 56 - interrupts 57 - clocks 58 - clock-names 59 - resets 60 - phys 61 - phy-names 62 63allOf: 64 - $ref: snps,dwc3.yaml# 65 66unevaluatedProperties: false 67 68examples: 69 - | 70 #include <dt-bindings/clock/aspeed,ast2700-scu.h> 71 #include <dt-bindings/reset/aspeed,ast2700-scu.h> 72 #include <dt-bindings/interrupt-controller/arm-gic.h> 73 74 bus { 75 #address-cells = <2>; 76 #size-cells = <2>; 77 78 usb@12030000 { 79 compatible = "aspeed,ast2700-xhci", "snps,dwc3"; 80 reg = <0x0 0x12030000 0x0 0x10000>; 81 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 82 clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>, 83 <&syscon0 SCU0_CLK_U2PHY_REFCLK>, 84 <&syscon0 SCU0_CLK_U2PHY_CLK12M>; 85 clock-names = "bus_early", "ref", "suspend"; 86 resets = <&syscon0 SCU0_RESET_PORTA_XHCI>; 87 pinctrl-names = "default"; 88 pinctrl-0 = <&pinctrl_usb3axh_default &pinctrl_usb2axh_default>; 89 phys = <&uphy3a>; 90 phy-names = "usb3-phy"; 91 dr_mode = "host"; 92 }; 93 }; 94