1*0ac067caSRyan Chen# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2*0ac067caSRyan Chen%YAML 1.2 3*0ac067caSRyan Chen--- 4*0ac067caSRyan Chen$id: http://devicetree.org/schemas/usb/aspeed,dwc3.yaml# 5*0ac067caSRyan Chen$schema: http://devicetree.org/meta-schemas/core.yaml# 6*0ac067caSRyan Chen 7*0ac067caSRyan Chentitle: Aspeed SuperSpeed DWC3 USB SoC controller 8*0ac067caSRyan Chen 9*0ac067caSRyan Chenmaintainers: 10*0ac067caSRyan Chen - Ryan Chen <ryan_chen@aspeedtech.com> 11*0ac067caSRyan Chen 12*0ac067caSRyan Chendescription: 13*0ac067caSRyan Chen The common content of the node is defined in snps,dwc3.yaml. 14*0ac067caSRyan Chen 15*0ac067caSRyan Chenselect: 16*0ac067caSRyan Chen properties: 17*0ac067caSRyan Chen compatible: 18*0ac067caSRyan Chen contains: 19*0ac067caSRyan Chen const: aspeed,ast2700-xhci 20*0ac067caSRyan Chen required: 21*0ac067caSRyan Chen - compatible 22*0ac067caSRyan Chen 23*0ac067caSRyan Chenproperties: 24*0ac067caSRyan Chen compatible: 25*0ac067caSRyan Chen items: 26*0ac067caSRyan Chen - const: aspeed,ast2700-xhci 27*0ac067caSRyan Chen - const: snps,dwc3 28*0ac067caSRyan Chen 29*0ac067caSRyan Chen interrupts: 30*0ac067caSRyan Chen maxItems: 1 31*0ac067caSRyan Chen 32*0ac067caSRyan Chen clocks: 33*0ac067caSRyan Chen items: 34*0ac067caSRyan Chen - description: Controller bus early clock 35*0ac067caSRyan Chen - description: PHY reference clock 36*0ac067caSRyan Chen - description: Controller suspend clock 37*0ac067caSRyan Chen 38*0ac067caSRyan Chen clock-names: 39*0ac067caSRyan Chen items: 40*0ac067caSRyan Chen - const: bus_early 41*0ac067caSRyan Chen - const: ref 42*0ac067caSRyan Chen - const: suspend 43*0ac067caSRyan Chen 44*0ac067caSRyan Chen resets: 45*0ac067caSRyan Chen maxItems: 1 46*0ac067caSRyan Chen 47*0ac067caSRyan Chen phys: 48*0ac067caSRyan Chen maxItems: 1 49*0ac067caSRyan Chen 50*0ac067caSRyan Chen phy-names: 51*0ac067caSRyan Chen const: usb3-phy 52*0ac067caSRyan Chen 53*0ac067caSRyan Chenrequired: 54*0ac067caSRyan Chen - compatible 55*0ac067caSRyan Chen - reg 56*0ac067caSRyan Chen - interrupts 57*0ac067caSRyan Chen - clocks 58*0ac067caSRyan Chen - clock-names 59*0ac067caSRyan Chen - resets 60*0ac067caSRyan Chen - phys 61*0ac067caSRyan Chen - phy-names 62*0ac067caSRyan Chen 63*0ac067caSRyan ChenallOf: 64*0ac067caSRyan Chen - $ref: snps,dwc3.yaml# 65*0ac067caSRyan Chen 66*0ac067caSRyan ChenunevaluatedProperties: false 67*0ac067caSRyan Chen 68*0ac067caSRyan Chenexamples: 69*0ac067caSRyan Chen - | 70*0ac067caSRyan Chen #include <dt-bindings/clock/aspeed,ast2700-scu.h> 71*0ac067caSRyan Chen #include <dt-bindings/reset/aspeed,ast2700-scu.h> 72*0ac067caSRyan Chen #include <dt-bindings/interrupt-controller/arm-gic.h> 73*0ac067caSRyan Chen 74*0ac067caSRyan Chen bus { 75*0ac067caSRyan Chen #address-cells = <2>; 76*0ac067caSRyan Chen #size-cells = <2>; 77*0ac067caSRyan Chen 78*0ac067caSRyan Chen usb@12030000 { 79*0ac067caSRyan Chen compatible = "aspeed,ast2700-xhci", "snps,dwc3"; 80*0ac067caSRyan Chen reg = <0x0 0x12030000 0x0 0x10000>; 81*0ac067caSRyan Chen interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 82*0ac067caSRyan Chen clocks = <&syscon0 SCU0_CLK_GATE_PORTAUSB2CLK>, 83*0ac067caSRyan Chen <&syscon0 SCU0_CLK_U2PHY_REFCLK>, 84*0ac067caSRyan Chen <&syscon0 SCU0_CLK_U2PHY_CLK12M>; 85*0ac067caSRyan Chen clock-names = "bus_early", "ref", "suspend"; 86*0ac067caSRyan Chen resets = <&syscon0 SCU0_RESET_PORTA_XHCI>; 87*0ac067caSRyan Chen pinctrl-names = "default"; 88*0ac067caSRyan Chen pinctrl-0 = <&pinctrl_usb3axh_default &pinctrl_usb2axh_default>; 89*0ac067caSRyan Chen phys = <&uphy3a>; 90*0ac067caSRyan Chen phy-names = "usb3-phy"; 91*0ac067caSRyan Chen dr_mode = "host"; 92*0ac067caSRyan Chen }; 93*0ac067caSRyan Chen }; 94