1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Universal Flash Storage (UFS) Controller 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 - Andy Gross <agross@kernel.org> 12 13# Select only our matches, not all jedec,ufs-2.0 14select: 15 properties: 16 compatible: 17 contains: 18 enum: 19 - qcom,msm8994-ufshc 20 - qcom,msm8996-ufshc 21 - qcom,qcs615-ufshc 22 - qcom,sdm845-ufshc 23 - qcom,sm6115-ufshc 24 - qcom,sm6125-ufshc 25 - qcom,sm6350-ufshc 26 - qcom,sm8150-ufshc 27 required: 28 - compatible 29 30properties: 31 compatible: 32 items: 33 - enum: 34 - qcom,msm8994-ufshc 35 - qcom,msm8996-ufshc 36 - qcom,qcs615-ufshc 37 - qcom,sdm845-ufshc 38 - qcom,sm6115-ufshc 39 - qcom,sm6125-ufshc 40 - qcom,sm6350-ufshc 41 - qcom,sm8150-ufshc 42 - const: qcom,ufshc 43 - const: jedec,ufs-2.0 44 45 qcom,ice: 46 $ref: /schemas/types.yaml#/definitions/phandle 47 description: phandle to the Inline Crypto Engine node 48 49 reg: 50 minItems: 1 51 maxItems: 2 52 53 reg-names: 54 items: 55 - const: std 56 - const: ice 57 58required: 59 - compatible 60 - reg 61 62allOf: 63 - $ref: qcom,ufs-common.yaml 64 65 - if: 66 properties: 67 compatible: 68 contains: 69 enum: 70 - qcom,sdm845-ufshc 71 - qcom,sm6350-ufshc 72 - qcom,sm8150-ufshc 73 then: 74 properties: 75 clocks: 76 minItems: 9 77 maxItems: 9 78 clock-names: 79 items: 80 - const: core_clk 81 - const: bus_aggr_clk 82 - const: iface_clk 83 - const: core_clk_unipro 84 - const: ref_clk 85 - const: tx_lane0_sync_clk 86 - const: rx_lane0_sync_clk 87 - const: rx_lane1_sync_clk 88 - const: ice_core_clk 89 reg: 90 minItems: 2 91 maxItems: 2 92 reg-names: 93 minItems: 2 94 required: 95 - reg-names 96 97 - if: 98 properties: 99 compatible: 100 contains: 101 enum: 102 - qcom,msm8996-ufshc 103 then: 104 properties: 105 clocks: 106 minItems: 9 107 maxItems: 9 108 clock-names: 109 items: 110 - const: core_clk 111 - const: bus_clk 112 - const: bus_aggr_clk 113 - const: iface_clk 114 - const: core_clk_unipro 115 - const: core_clk_ice 116 - const: ref_clk 117 - const: tx_lane0_sync_clk 118 - const: rx_lane0_sync_clk 119 reg: 120 minItems: 1 121 maxItems: 1 122 reg-names: 123 maxItems: 1 124 125 - if: 126 properties: 127 compatible: 128 contains: 129 enum: 130 - qcom,qcs615-ufshc 131 - qcom,sm6115-ufshc 132 - qcom,sm6125-ufshc 133 then: 134 properties: 135 clocks: 136 minItems: 8 137 maxItems: 8 138 clock-names: 139 items: 140 - const: core_clk 141 - const: bus_aggr_clk 142 - const: iface_clk 143 - const: core_clk_unipro 144 - const: ref_clk 145 - const: tx_lane0_sync_clk 146 - const: rx_lane0_sync_clk 147 - const: ice_core_clk 148 reg: 149 minItems: 2 150 maxItems: 2 151 reg-names: 152 minItems: 2 153 required: 154 - reg-names 155 156 # TODO: define clock bindings for qcom,msm8994-ufshc 157 158 - if: 159 required: 160 - qcom,ice 161 then: 162 properties: 163 reg: 164 maxItems: 1 165 clocks: 166 minItems: 7 167 maxItems: 8 168 else: 169 properties: 170 reg: 171 minItems: 1 172 maxItems: 2 173 clocks: 174 minItems: 7 175 maxItems: 9 176 177unevaluatedProperties: false 178 179examples: 180 - | 181 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 182 #include <dt-bindings/clock/qcom,rpmh.h> 183 #include <dt-bindings/gpio/gpio.h> 184 #include <dt-bindings/interconnect/qcom,sm8150.h> 185 #include <dt-bindings/interrupt-controller/arm-gic.h> 186 187 soc { 188 #address-cells = <2>; 189 #size-cells = <2>; 190 191 ufs@1d84000 { 192 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 193 "jedec,ufs-2.0"; 194 reg = <0x0 0x01d84000 0x0 0x2500>, 195 <0x0 0x01d90000 0x0 0x8000>; 196 reg-names = "std", "ice"; 197 198 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 199 phys = <&ufs_mem_phy_lanes>; 200 phy-names = "ufsphy"; 201 lanes-per-direction = <2>; 202 #reset-cells = <1>; 203 resets = <&gcc GCC_UFS_PHY_BCR>; 204 reset-names = "rst"; 205 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; 206 207 vcc-supply = <&vreg_l7b_2p5>; 208 vcc-max-microamp = <1100000>; 209 vccq-supply = <&vreg_l9b_1p2>; 210 vccq-max-microamp = <1200000>; 211 212 power-domains = <&gcc UFS_PHY_GDSC>; 213 iommus = <&apps_smmu 0x300 0>; 214 215 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 216 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 217 <&gcc GCC_UFS_PHY_AHB_CLK>, 218 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 219 <&rpmhcc RPMH_CXO_CLK>, 220 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 221 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 222 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 223 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 224 clock-names = "core_clk", 225 "bus_aggr_clk", 226 "iface_clk", 227 "core_clk_unipro", 228 "ref_clk", 229 "tx_lane0_sync_clk", 230 "rx_lane0_sync_clk", 231 "rx_lane1_sync_clk", 232 "ice_core_clk"; 233 freq-table-hz = <37500000 300000000>, 234 <0 0>, 235 <0 0>, 236 <37500000 300000000>, 237 <0 0>, 238 <0 0>, 239 <0 0>, 240 <0 0>, 241 <0 300000000>; 242 }; 243 }; 244