1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Universal Flash Storage (UFS) Controller 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 - Andy Gross <agross@kernel.org> 12 13# Select only our matches, not all jedec,ufs-2.0 14select: 15 properties: 16 compatible: 17 contains: 18 enum: 19 - qcom,msm8994-ufshc 20 - qcom,msm8996-ufshc 21 - qcom,qcs615-ufshc 22 - qcom,sdm845-ufshc 23 - qcom,sm6115-ufshc 24 - qcom,sm6125-ufshc 25 - qcom,sm6350-ufshc 26 - qcom,sm8150-ufshc 27 required: 28 - compatible 29 30properties: 31 compatible: 32 items: 33 - enum: 34 - qcom,msm8994-ufshc 35 - qcom,msm8996-ufshc 36 - qcom,qcs615-ufshc 37 - qcom,sdm845-ufshc 38 - qcom,sm6115-ufshc 39 - qcom,sm6125-ufshc 40 - qcom,sm6350-ufshc 41 - qcom,sm8150-ufshc 42 - const: qcom,ufshc 43 - const: jedec,ufs-2.0 44 45 qcom,ice: 46 $ref: /schemas/types.yaml#/definitions/phandle 47 description: phandle to the Inline Crypto Engine node 48 49 reg: 50 minItems: 1 51 maxItems: 2 52 53 reg-names: 54 items: 55 - const: std 56 - const: ice 57 58required: 59 - compatible 60 - reg 61 62allOf: 63 - $ref: qcom,ufs-common.yaml 64 65 - if: 66 properties: 67 compatible: 68 contains: 69 enum: 70 - qcom,sdm845-ufshc 71 - qcom,sm6350-ufshc 72 - qcom,sm8150-ufshc 73 then: 74 properties: 75 clocks: 76 minItems: 9 77 maxItems: 9 78 clock-names: 79 items: 80 - const: core_clk 81 - const: bus_aggr_clk 82 - const: iface_clk 83 - const: core_clk_unipro 84 - const: ref_clk 85 - const: tx_lane0_sync_clk 86 - const: rx_lane0_sync_clk 87 - const: rx_lane1_sync_clk 88 - const: ice_core_clk 89 reg: 90 minItems: 2 91 reg-names: 92 minItems: 2 93 required: 94 - reg-names 95 96 - if: 97 properties: 98 compatible: 99 contains: 100 enum: 101 - qcom,msm8996-ufshc 102 then: 103 properties: 104 clocks: 105 minItems: 9 106 maxItems: 9 107 clock-names: 108 items: 109 - const: core_clk 110 - const: bus_clk 111 - const: bus_aggr_clk 112 - const: iface_clk 113 - const: core_clk_unipro 114 - const: core_clk_ice 115 - const: ref_clk 116 - const: tx_lane0_sync_clk 117 - const: rx_lane0_sync_clk 118 reg: 119 maxItems: 1 120 reg-names: 121 maxItems: 1 122 123 - if: 124 properties: 125 compatible: 126 contains: 127 enum: 128 - qcom,qcs615-ufshc 129 - qcom,sm6115-ufshc 130 - qcom,sm6125-ufshc 131 then: 132 properties: 133 clocks: 134 minItems: 8 135 maxItems: 8 136 clock-names: 137 items: 138 - const: core_clk 139 - const: bus_aggr_clk 140 - const: iface_clk 141 - const: core_clk_unipro 142 - const: ref_clk 143 - const: tx_lane0_sync_clk 144 - const: rx_lane0_sync_clk 145 - const: ice_core_clk 146 reg: 147 minItems: 2 148 reg-names: 149 minItems: 2 150 required: 151 - reg-names 152 153 # TODO: define clock bindings for qcom,msm8994-ufshc 154 155 - if: 156 required: 157 - qcom,ice 158 then: 159 properties: 160 reg: 161 maxItems: 1 162 clocks: 163 minItems: 7 164 maxItems: 8 165 else: 166 properties: 167 reg: 168 minItems: 1 169 maxItems: 2 170 clocks: 171 minItems: 7 172 maxItems: 9 173 174unevaluatedProperties: false 175 176examples: 177 - | 178 #include <dt-bindings/clock/qcom,gcc-sm8150.h> 179 #include <dt-bindings/clock/qcom,rpmh.h> 180 #include <dt-bindings/gpio/gpio.h> 181 #include <dt-bindings/interconnect/qcom,sm8150.h> 182 #include <dt-bindings/interrupt-controller/arm-gic.h> 183 184 soc { 185 #address-cells = <2>; 186 #size-cells = <2>; 187 188 ufs@1d84000 { 189 compatible = "qcom,sm8150-ufshc", "qcom,ufshc", 190 "jedec,ufs-2.0"; 191 reg = <0x0 0x01d84000 0x0 0x2500>, 192 <0x0 0x01d90000 0x0 0x8000>; 193 reg-names = "std", "ice"; 194 195 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 196 phys = <&ufs_mem_phy_lanes>; 197 phy-names = "ufsphy"; 198 lanes-per-direction = <2>; 199 #reset-cells = <1>; 200 resets = <&gcc GCC_UFS_PHY_BCR>; 201 reset-names = "rst"; 202 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; 203 204 vcc-supply = <&vreg_l7b_2p5>; 205 vcc-max-microamp = <1100000>; 206 vccq-supply = <&vreg_l9b_1p2>; 207 vccq-max-microamp = <1200000>; 208 209 power-domains = <&gcc UFS_PHY_GDSC>; 210 iommus = <&apps_smmu 0x300 0>; 211 212 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 213 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 214 <&gcc GCC_UFS_PHY_AHB_CLK>, 215 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 216 <&rpmhcc RPMH_CXO_CLK>, 217 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 218 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 219 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>, 220 <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 221 clock-names = "core_clk", 222 "bus_aggr_clk", 223 "iface_clk", 224 "core_clk_unipro", 225 "ref_clk", 226 "tx_lane0_sync_clk", 227 "rx_lane0_sync_clk", 228 "rx_lane1_sync_clk", 229 "ice_core_clk"; 230 freq-table-hz = <37500000 300000000>, 231 <0 0>, 232 <0 0>, 233 <37500000 300000000>, 234 <0 0>, 235 <0 0>, 236 <0 0>, 237 <0 0>, 238 <0 300000000>; 239 }; 240 }; 241