1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Universal Flash Storage (UFS) Controller 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 - Andy Gross <agross@kernel.org> 12 13# Select only our matches, not all jedec,ufs-2.0 14select: 15 properties: 16 compatible: 17 contains: 18 const: qcom,ufshc 19 required: 20 - compatible 21 22properties: 23 compatible: 24 items: 25 - enum: 26 - qcom,msm8994-ufshc 27 - qcom,msm8996-ufshc 28 - qcom,msm8998-ufshc 29 - qcom,qcs8300-ufshc 30 - qcom,sa8775p-ufshc 31 - qcom,sc7180-ufshc 32 - qcom,sc7280-ufshc 33 - qcom,sc8180x-ufshc 34 - qcom,sc8280xp-ufshc 35 - qcom,sdm845-ufshc 36 - qcom,sm6115-ufshc 37 - qcom,sm6125-ufshc 38 - qcom,sm6350-ufshc 39 - qcom,sm8150-ufshc 40 - qcom,sm8250-ufshc 41 - qcom,sm8350-ufshc 42 - qcom,sm8450-ufshc 43 - qcom,sm8550-ufshc 44 - qcom,sm8650-ufshc 45 - const: qcom,ufshc 46 - const: jedec,ufs-2.0 47 48 clocks: 49 minItems: 7 50 maxItems: 9 51 52 clock-names: 53 minItems: 7 54 maxItems: 9 55 56 dma-coherent: true 57 58 interconnects: 59 minItems: 2 60 maxItems: 2 61 62 interconnect-names: 63 items: 64 - const: ufs-ddr 65 - const: cpu-ufs 66 67 iommus: 68 minItems: 1 69 maxItems: 2 70 71 phys: 72 maxItems: 1 73 74 phy-names: 75 items: 76 - const: ufsphy 77 78 power-domains: 79 maxItems: 1 80 81 qcom,ice: 82 $ref: /schemas/types.yaml#/definitions/phandle 83 description: phandle to the Inline Crypto Engine node 84 85 reg: 86 minItems: 1 87 maxItems: 2 88 89 reg-names: 90 items: 91 - const: std 92 - const: ice 93 94 required-opps: 95 maxItems: 1 96 97 resets: 98 maxItems: 1 99 100 '#reset-cells': 101 const: 1 102 103 reset-names: 104 items: 105 - const: rst 106 107 reset-gpios: 108 maxItems: 1 109 description: 110 GPIO connected to the RESET pin of the UFS memory device. 111 112required: 113 - compatible 114 - reg 115 116allOf: 117 - $ref: ufs-common.yaml 118 119 - if: 120 properties: 121 compatible: 122 contains: 123 enum: 124 - qcom,sc7180-ufshc 125 then: 126 properties: 127 clocks: 128 minItems: 7 129 maxItems: 7 130 clock-names: 131 items: 132 - const: core_clk 133 - const: bus_aggr_clk 134 - const: iface_clk 135 - const: core_clk_unipro 136 - const: ref_clk 137 - const: tx_lane0_sync_clk 138 - const: rx_lane0_sync_clk 139 reg: 140 maxItems: 1 141 reg-names: 142 maxItems: 1 143 144 - if: 145 properties: 146 compatible: 147 contains: 148 enum: 149 - qcom,msm8998-ufshc 150 - qcom,qcs8300-ufshc 151 - qcom,sa8775p-ufshc 152 - qcom,sc7280-ufshc 153 - qcom,sc8180x-ufshc 154 - qcom,sc8280xp-ufshc 155 - qcom,sm8250-ufshc 156 - qcom,sm8350-ufshc 157 - qcom,sm8450-ufshc 158 - qcom,sm8550-ufshc 159 - qcom,sm8650-ufshc 160 then: 161 properties: 162 clocks: 163 minItems: 8 164 maxItems: 8 165 clock-names: 166 items: 167 - const: core_clk 168 - const: bus_aggr_clk 169 - const: iface_clk 170 - const: core_clk_unipro 171 - const: ref_clk 172 - const: tx_lane0_sync_clk 173 - const: rx_lane0_sync_clk 174 - const: rx_lane1_sync_clk 175 reg: 176 minItems: 1 177 maxItems: 1 178 reg-names: 179 maxItems: 1 180 181 - if: 182 properties: 183 compatible: 184 contains: 185 enum: 186 - qcom,sdm845-ufshc 187 - qcom,sm6350-ufshc 188 - qcom,sm8150-ufshc 189 then: 190 properties: 191 clocks: 192 minItems: 9 193 maxItems: 9 194 clock-names: 195 items: 196 - const: core_clk 197 - const: bus_aggr_clk 198 - const: iface_clk 199 - const: core_clk_unipro 200 - const: ref_clk 201 - const: tx_lane0_sync_clk 202 - const: rx_lane0_sync_clk 203 - const: rx_lane1_sync_clk 204 - const: ice_core_clk 205 reg: 206 minItems: 2 207 maxItems: 2 208 reg-names: 209 minItems: 2 210 required: 211 - reg-names 212 213 - if: 214 properties: 215 compatible: 216 contains: 217 enum: 218 - qcom,msm8996-ufshc 219 then: 220 properties: 221 clocks: 222 minItems: 9 223 maxItems: 9 224 clock-names: 225 items: 226 - const: core_clk 227 - const: bus_clk 228 - const: bus_aggr_clk 229 - const: iface_clk 230 - const: core_clk_unipro 231 - const: core_clk_ice 232 - const: ref_clk 233 - const: tx_lane0_sync_clk 234 - const: rx_lane0_sync_clk 235 reg: 236 minItems: 1 237 maxItems: 1 238 reg-names: 239 maxItems: 1 240 241 - if: 242 properties: 243 compatible: 244 contains: 245 enum: 246 - qcom,sm6115-ufshc 247 - qcom,sm6125-ufshc 248 then: 249 properties: 250 clocks: 251 minItems: 8 252 maxItems: 8 253 clock-names: 254 items: 255 - const: core_clk 256 - const: bus_aggr_clk 257 - const: iface_clk 258 - const: core_clk_unipro 259 - const: ref_clk 260 - const: tx_lane0_sync_clk 261 - const: rx_lane0_sync_clk 262 - const: ice_core_clk 263 reg: 264 minItems: 2 265 maxItems: 2 266 reg-names: 267 minItems: 2 268 required: 269 - reg-names 270 271 # TODO: define clock bindings for qcom,msm8994-ufshc 272 273 - if: 274 required: 275 - qcom,ice 276 then: 277 properties: 278 reg: 279 maxItems: 1 280 clocks: 281 minItems: 7 282 maxItems: 8 283 else: 284 properties: 285 reg: 286 minItems: 1 287 maxItems: 2 288 clocks: 289 minItems: 7 290 maxItems: 9 291 292unevaluatedProperties: false 293 294examples: 295 - | 296 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 297 #include <dt-bindings/clock/qcom,rpmh.h> 298 #include <dt-bindings/gpio/gpio.h> 299 #include <dt-bindings/interconnect/qcom,sm8450.h> 300 #include <dt-bindings/interrupt-controller/arm-gic.h> 301 302 soc { 303 #address-cells = <2>; 304 #size-cells = <2>; 305 306 ufs@1d84000 { 307 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 308 "jedec,ufs-2.0"; 309 reg = <0 0x01d84000 0 0x3000>; 310 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 311 phys = <&ufs_mem_phy_lanes>; 312 phy-names = "ufsphy"; 313 lanes-per-direction = <2>; 314 #reset-cells = <1>; 315 resets = <&gcc GCC_UFS_PHY_BCR>; 316 reset-names = "rst"; 317 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; 318 319 vcc-supply = <&vreg_l7b_2p5>; 320 vcc-max-microamp = <1100000>; 321 vccq-supply = <&vreg_l9b_1p2>; 322 vccq-max-microamp = <1200000>; 323 324 power-domains = <&gcc UFS_PHY_GDSC>; 325 iommus = <&apps_smmu 0xe0 0x0>; 326 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, 327 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; 328 interconnect-names = "ufs-ddr", "cpu-ufs"; 329 330 clock-names = "core_clk", 331 "bus_aggr_clk", 332 "iface_clk", 333 "core_clk_unipro", 334 "ref_clk", 335 "tx_lane0_sync_clk", 336 "rx_lane0_sync_clk", 337 "rx_lane1_sync_clk"; 338 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 339 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 340 <&gcc GCC_UFS_PHY_AHB_CLK>, 341 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 342 <&rpmhcc RPMH_CXO_CLK>, 343 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 344 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 345 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 346 freq-table-hz = <75000000 300000000>, 347 <0 0>, 348 <0 0>, 349 <75000000 300000000>, 350 <75000000 300000000>, 351 <0 0>, 352 <0 0>, 353 <0 0>; 354 qcom,ice = <&ice>; 355 }; 356 }; 357