1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/ufs/qcom,ufs.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Qualcomm Universal Flash Storage (UFS) Controller 8 9maintainers: 10 - Bjorn Andersson <bjorn.andersson@linaro.org> 11 - Andy Gross <agross@kernel.org> 12 13# Select only our matches, not all jedec,ufs-2.0 14select: 15 properties: 16 compatible: 17 contains: 18 const: qcom,ufshc 19 required: 20 - compatible 21 22properties: 23 compatible: 24 items: 25 - enum: 26 - qcom,msm8994-ufshc 27 - qcom,msm8996-ufshc 28 - qcom,msm8998-ufshc 29 - qcom,sa8775p-ufshc 30 - qcom,sc8280xp-ufshc 31 - qcom,sdm845-ufshc 32 - qcom,sm6350-ufshc 33 - qcom,sm8150-ufshc 34 - qcom,sm8250-ufshc 35 - qcom,sm8350-ufshc 36 - qcom,sm8450-ufshc 37 - qcom,sm8550-ufshc 38 - const: qcom,ufshc 39 - const: jedec,ufs-2.0 40 41 clocks: 42 minItems: 8 43 maxItems: 11 44 45 clock-names: 46 minItems: 8 47 maxItems: 11 48 49 dma-coherent: true 50 51 interconnects: 52 minItems: 2 53 maxItems: 2 54 55 interconnect-names: 56 items: 57 - const: ufs-ddr 58 - const: cpu-ufs 59 60 iommus: 61 minItems: 1 62 maxItems: 2 63 64 phys: 65 maxItems: 1 66 67 phy-names: 68 items: 69 - const: ufsphy 70 71 power-domains: 72 maxItems: 1 73 74 qcom,ice: 75 $ref: /schemas/types.yaml#/definitions/phandle 76 description: phandle to the Inline Crypto Engine node 77 78 reg: 79 minItems: 1 80 maxItems: 2 81 82 required-opps: 83 maxItems: 1 84 85 resets: 86 maxItems: 1 87 88 '#reset-cells': 89 const: 1 90 91 reset-names: 92 items: 93 - const: rst 94 95 reset-gpios: 96 maxItems: 1 97 description: 98 GPIO connected to the RESET pin of the UFS memory device. 99 100required: 101 - compatible 102 - reg 103 104allOf: 105 - $ref: ufs-common.yaml 106 107 - if: 108 properties: 109 compatible: 110 contains: 111 enum: 112 - qcom,msm8998-ufshc 113 - qcom,sa8775p-ufshc 114 - qcom,sc8280xp-ufshc 115 - qcom,sm8250-ufshc 116 - qcom,sm8350-ufshc 117 - qcom,sm8450-ufshc 118 - qcom,sm8550-ufshc 119 then: 120 properties: 121 clocks: 122 minItems: 8 123 maxItems: 8 124 clock-names: 125 items: 126 - const: core_clk 127 - const: bus_aggr_clk 128 - const: iface_clk 129 - const: core_clk_unipro 130 - const: ref_clk 131 - const: tx_lane0_sync_clk 132 - const: rx_lane0_sync_clk 133 - const: rx_lane1_sync_clk 134 reg: 135 minItems: 1 136 maxItems: 1 137 138 - if: 139 properties: 140 compatible: 141 contains: 142 enum: 143 - qcom,sdm845-ufshc 144 - qcom,sm6350-ufshc 145 - qcom,sm8150-ufshc 146 then: 147 properties: 148 clocks: 149 minItems: 9 150 maxItems: 9 151 clock-names: 152 items: 153 - const: core_clk 154 - const: bus_aggr_clk 155 - const: iface_clk 156 - const: core_clk_unipro 157 - const: ref_clk 158 - const: tx_lane0_sync_clk 159 - const: rx_lane0_sync_clk 160 - const: rx_lane1_sync_clk 161 - const: ice_core_clk 162 reg: 163 minItems: 2 164 maxItems: 2 165 166 - if: 167 properties: 168 compatible: 169 contains: 170 enum: 171 - qcom,msm8996-ufshc 172 then: 173 properties: 174 clocks: 175 minItems: 11 176 maxItems: 11 177 clock-names: 178 items: 179 - const: core_clk_src 180 - const: core_clk 181 - const: bus_clk 182 - const: bus_aggr_clk 183 - const: iface_clk 184 - const: core_clk_unipro_src 185 - const: core_clk_unipro 186 - const: core_clk_ice 187 - const: ref_clk 188 - const: tx_lane0_sync_clk 189 - const: rx_lane0_sync_clk 190 reg: 191 minItems: 1 192 maxItems: 1 193 194 # TODO: define clock bindings for qcom,msm8994-ufshc 195 196 - if: 197 required: 198 - qcom,ice 199 then: 200 properties: 201 reg: 202 maxItems: 1 203 clocks: 204 minItems: 8 205 maxItems: 8 206 else: 207 properties: 208 reg: 209 minItems: 1 210 maxItems: 2 211 clocks: 212 minItems: 8 213 maxItems: 11 214 215unevaluatedProperties: false 216 217examples: 218 - | 219 #include <dt-bindings/clock/qcom,gcc-sm8450.h> 220 #include <dt-bindings/clock/qcom,rpmh.h> 221 #include <dt-bindings/gpio/gpio.h> 222 #include <dt-bindings/interconnect/qcom,sm8450.h> 223 #include <dt-bindings/interrupt-controller/arm-gic.h> 224 225 soc { 226 #address-cells = <2>; 227 #size-cells = <2>; 228 229 ufs@1d84000 { 230 compatible = "qcom,sm8450-ufshc", "qcom,ufshc", 231 "jedec,ufs-2.0"; 232 reg = <0 0x01d84000 0 0x3000>; 233 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 234 phys = <&ufs_mem_phy_lanes>; 235 phy-names = "ufsphy"; 236 lanes-per-direction = <2>; 237 #reset-cells = <1>; 238 resets = <&gcc GCC_UFS_PHY_BCR>; 239 reset-names = "rst"; 240 reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>; 241 242 vcc-supply = <&vreg_l7b_2p5>; 243 vcc-max-microamp = <1100000>; 244 vccq-supply = <&vreg_l9b_1p2>; 245 vccq-max-microamp = <1200000>; 246 247 power-domains = <&gcc UFS_PHY_GDSC>; 248 iommus = <&apps_smmu 0xe0 0x0>; 249 interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, 250 <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; 251 interconnect-names = "ufs-ddr", "cpu-ufs"; 252 253 clock-names = "core_clk", 254 "bus_aggr_clk", 255 "iface_clk", 256 "core_clk_unipro", 257 "ref_clk", 258 "tx_lane0_sync_clk", 259 "rx_lane0_sync_clk", 260 "rx_lane1_sync_clk"; 261 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 262 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 263 <&gcc GCC_UFS_PHY_AHB_CLK>, 264 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 265 <&rpmhcc RPMH_CXO_CLK>, 266 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 267 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 268 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 269 freq-table-hz = <75000000 300000000>, 270 <0 0>, 271 <0 0>, 272 <75000000 300000000>, 273 <75000000 300000000>, 274 <0 0>, 275 <0 0>, 276 <0 0>; 277 }; 278 }; 279