xref: /linux/Documentation/devicetree/bindings/ufs/hisilicon,ufs.yaml (revision ed5c2f5fd10dda07263f79f338a512c0f49f76f5) 
1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/ufs/hisilicon,ufs.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: HiSilicon Universal Flash Storage (UFS) Controller
8
9maintainers:
10  - Li Wei <liwei213@huawei.com>
11
12# Select only our matches, not all jedec,ufs
13select:
14  properties:
15    compatible:
16      contains:
17        enum:
18          - hisilicon,hi3660-ufs
19          - hisilicon,hi3670-ufs
20  required:
21    - compatible
22
23allOf:
24  - $ref: ufs-common.yaml
25
26properties:
27  compatible:
28    oneOf:
29      - items:
30          - const: hisilicon,hi3660-ufs
31          - const: jedec,ufs-1.1
32      - items:
33          - enum:
34              - hisilicon,hi3670-ufs
35          - const: jedec,ufs-2.1
36
37  clocks:
38    minItems: 2
39    maxItems: 2
40
41  clock-names:
42    items:
43      - const: ref_clk
44      - const: phy_clk
45
46  reg:
47    items:
48      - description: UFS register address space
49      - description: UFS SYS CTRL register address space
50
51  resets:
52    maxItems: 1
53
54  reset-names:
55    items:
56      - const: rst
57
58required:
59  - compatible
60  - reg
61  - resets
62  - reset-names
63
64unevaluatedProperties: false
65
66examples:
67  - |
68    #include <dt-bindings/clock/hi3670-clock.h>
69    #include <dt-bindings/interrupt-controller/arm-gic.h>
70
71    soc {
72        #address-cells = <2>;
73        #size-cells = <2>;
74
75        ufs@ff3c0000 {
76            compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
77            reg = <0x0 0xff3c0000 0x0 0x1000>,
78                  <0x0 0xff3e0000 0x0 0x1000>;
79            interrupt-parent = <&gic>;
80            interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
81            clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
82                     <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
83            clock-names = "ref_clk", "phy_clk";
84            freq-table-hz = <0 0>,
85                            <0 0>;
86
87            resets = <&crg_rst 0x84 12>;
88            reset-names = "rst";
89        };
90    };
91