xref: /linux/Documentation/devicetree/bindings/timestamp/nvidia,tegra194-hte.yaml (revision fbf5df34a4dbcd09d433dd4f0916bf9b2ddb16de) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timestamp/nvidia,tegra194-hte.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Tegra on chip generic hardware timestamping engine (HTE) provider
8
9maintainers:
10  - Dipen Patel <dipenp@nvidia.com>
11
12description:
13  Tegra SoC has two instances of generic hardware timestamping engines (GTE)
14  known as GTE GPIO and GTE IRQ, which can monitor subset of GPIO and on chip
15  IRQ lines for the state change respectively, upon detection it will record
16  timestamp (taken from system counter) in its internal hardware FIFO. It has
17  a bitmap array arranged in 32bit slices where each bit represent signal/line
18  to enable or disable for the hardware timestamping. The GTE GPIO monitors
19  GPIO lines from the AON (always on) GPIO controller.
20
21properties:
22  compatible:
23    enum:
24      - nvidia,tegra194-gte-aon
25      - nvidia,tegra194-gte-lic
26      - nvidia,tegra234-gte-aon
27      - nvidia,tegra234-gte-lic
28      - nvidia,tegra264-gte-aon
29      - nvidia,tegra264-gte-lic
30
31  reg:
32    maxItems: 1
33
34  interrupts:
35    maxItems: 1
36
37  nvidia,int-threshold:
38    $ref: /schemas/types.yaml#/definitions/uint32
39    description:
40      HTE device generates its interrupt based on this u32 FIFO threshold
41      value. The recommended value is 1.
42    minimum: 1
43    maximum: 256
44
45  nvidia,slices:
46    $ref: /schemas/types.yaml#/definitions/uint32
47    deprecated: true
48    description:
49      HTE lines are arranged in 32 bit slice where each bit represents different
50      line/signal that it can enable/configure for the timestamp. It is u32
51      property and the value depends on the HTE instance in the chip. The AON
52      GTE instances for both Tegra194 and Tegra234 has 3 slices. The Tegra194
53      LIC instance has 11 slices and Tegra234 LIC has 17 slices.
54    enum: [3, 11, 17]
55
56  nvidia,gpio-controller:
57    $ref: /schemas/types.yaml#/definitions/phandle
58    description:
59      The phandle to AON gpio controller instance. This is required to handle
60      namespace conversion between GPIO and GTE.
61
62  '#timestamp-cells':
63    description:
64      This represents number of line id arguments as specified by the
65      consumers. For the GTE IRQ, this is IRQ number as mentioned in the
66      SoC technical reference manual. For the GTE GPIO, its value is same as
67      mentioned in the nvidia GPIO device tree binding document.
68    const: 1
69
70required:
71  - compatible
72  - reg
73  - interrupts
74  - "#timestamp-cells"
75
76allOf:
77  - if:
78      properties:
79        compatible:
80          contains:
81            enum:
82              - nvidia,tegra194-gte-aon
83              - nvidia,tegra234-gte-aon
84    then:
85      properties:
86        nvidia,slices:
87          const: 3
88
89  - if:
90      properties:
91        compatible:
92          contains:
93            enum:
94              - nvidia,tegra194-gte-lic
95    then:
96      properties:
97        nvidia,slices:
98          const: 11
99
100  - if:
101      properties:
102        compatible:
103          contains:
104            enum:
105              - nvidia,tegra234-gte-lic
106    then:
107      properties:
108        nvidia,slices:
109          const: 17
110
111  - if:
112      properties:
113        compatible:
114          contains:
115            enum:
116              - nvidia,tegra234-gte-aon
117              - nvidia,tegra264-gte-aon
118    then:
119      required:
120        - nvidia,gpio-controller
121
122  - if:
123      properties:
124        compatible:
125          contains:
126            enum:
127              - nvidia,tegra264-gte-aon
128              - nvidia,tegra264-gte-lic
129    then:
130      properties:
131        nvidia,slices: false
132
133additionalProperties: false
134
135examples:
136  - |
137    tegra_hte_aon: timestamp@c1e0000 {
138              compatible = "nvidia,tegra194-gte-aon";
139              reg = <0xc1e0000 0x10000>;
140              interrupts = <0 13 0x4>;
141              nvidia,int-threshold = <1>;
142              #timestamp-cells = <1>;
143    };
144
145  - |
146    tegra_hte_lic: timestamp@3aa0000 {
147              compatible = "nvidia,tegra194-gte-lic";
148              reg = <0x3aa0000 0x10000>;
149              interrupts = <0 11 0x4>;
150              nvidia,int-threshold = <1>;
151              #timestamp-cells = <1>;
152    };
153
154...
155