xref: /linux/Documentation/devicetree/bindings/timer/sifive,clint.yaml (revision c17ee635fd3a482b2ad2bf5e269755c2eae5f25e) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive Core Local Interruptor
8
9maintainers:
10  - Palmer Dabbelt <palmer@dabbelt.com>
11  - Anup Patel <anup.patel@wdc.com>
12
13description:
14  SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15  Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16  interrupts. It directly connects to the timer and inter-processor interrupt
17  lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18  interrupt controller is the parent interrupt controller for CLINT device.
19  The clock frequency of CLINT is specified via "timebase-frequency" DT
20  property of "/cpus" DT node. The "timebase-frequency" DT property is
21  described in Documentation/devicetree/bindings/riscv/cpus.yaml
22
23  T-Head C906/C910 CPU cores include an implementation of CLINT too, however
24  their implementation lacks a memory-mapped MTIME register, thus not
25  compatible with SiFive ones.
26
27properties:
28  compatible:
29    oneOf:
30      - items:
31          - enum:
32              - canaan,k210-clint       # Canaan Kendryte K210
33              - eswin,eic7700-clint     # ESWIN EIC7700
34              - sifive,fu540-c000-clint # SiFive FU540
35              - spacemit,k1-clint       # SpacemiT K1
36              - spacemit,k3-clint       # SpacemiT K3
37              - starfive,jh7100-clint   # StarFive JH7100
38              - starfive,jh7110-clint   # StarFive JH7110
39              - starfive,jh8100-clint   # StarFive JH8100
40              - tenstorrent,blackhole-clint # Tenstorrent Blackhole
41          - const: sifive,clint0        # SiFive CLINT v0 IP block
42      - items:
43          - {}
44          - const: sifive,clint2        # SiFive CLINT v2 IP block
45        description:
46          SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
47          differs from that of sifive,clint0, making them incompatible.
48      - items:
49          - enum:
50              - allwinner,sun20i-d1-clint
51              - sophgo,cv1800b-clint
52              - sophgo,cv1812h-clint
53              - sophgo,sg2002-clint
54              - thead,th1520-clint
55          - const: thead,c900-clint
56      - items:
57          - const: sifive,clint0
58          - const: riscv,clint0
59        deprecated: true
60        description: For the QEMU virt machine only
61
62    description:
63      Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
64      when compatible with a SiFive CLINT.  Please refer to
65      sifive-blocks-ip-versioning.txt for details regarding the latter.
66
67  reg:
68    maxItems: 1
69
70  interrupts-extended:
71    minItems: 1
72    maxItems: 4095
73
74  sifive,fine-ctr-bits:
75    maximum: 15
76    description: The width in bits of the fine counter.
77
78if:
79  properties:
80    compatible:
81      contains:
82        const: sifive,clint2
83then:
84  required:
85    - sifive,fine-ctr-bits
86else:
87  properties:
88    sifive,fine-ctr-bits: false
89
90additionalProperties: false
91
92required:
93  - compatible
94  - reg
95  - interrupts-extended
96
97examples:
98  - |
99    timer@2000000 {
100      compatible = "sifive,fu540-c000-clint", "sifive,clint0";
101      interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
102                            <&cpu2intc 3>, <&cpu2intc 7>,
103                            <&cpu3intc 3>, <&cpu3intc 7>,
104                            <&cpu4intc 3>, <&cpu4intc 7>;
105      reg = <0x2000000 0x10000>;
106    };
107...
108