xref: /linux/Documentation/devicetree/bindings/timer/sifive,clint.yaml (revision 53597deca0e38c30e6cd4ba2114fa42d2bcd85bb) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive Core Local Interruptor
8
9maintainers:
10  - Palmer Dabbelt <palmer@dabbelt.com>
11  - Anup Patel <anup.patel@wdc.com>
12
13description:
14  SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15  Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16  interrupts. It directly connects to the timer and inter-processor interrupt
17  lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18  interrupt controller is the parent interrupt controller for CLINT device.
19  The clock frequency of CLINT is specified via "timebase-frequency" DT
20  property of "/cpus" DT node. The "timebase-frequency" DT property is
21  described in Documentation/devicetree/bindings/riscv/cpus.yaml
22
23  T-Head C906/C910 CPU cores include an implementation of CLINT too, however
24  their implementation lacks a memory-mapped MTIME register, thus not
25  compatible with SiFive ones.
26
27properties:
28  compatible:
29    oneOf:
30      - items:
31          - enum:
32              - canaan,k210-clint       # Canaan Kendryte K210
33              - eswin,eic7700-clint     # ESWIN EIC7700
34              - microchip,pic64gx-clint # Microchip PIC64GX
35              - sifive,fu540-c000-clint # SiFive FU540
36              - spacemit,k1-clint       # SpacemiT K1
37              - spacemit,k3-clint       # SpacemiT K3
38              - starfive,jh7100-clint   # StarFive JH7100
39              - starfive,jh7110-clint   # StarFive JH7110
40              - starfive,jh8100-clint   # StarFive JH8100
41              - tenstorrent,blackhole-clint # Tenstorrent Blackhole
42          - const: sifive,clint0        # SiFive CLINT v0 IP block
43      - items:
44          - {}
45          - const: sifive,clint2        # SiFive CLINT v2 IP block
46        description:
47          SiFive CLINT v2 is the HRT that supports the Zicntr. The control of sifive,clint2
48          differs from that of sifive,clint0, making them incompatible.
49      - items:
50          - enum:
51              - allwinner,sun20i-d1-clint
52              - sophgo,cv1800b-clint
53              - sophgo,cv1812h-clint
54              - sophgo,sg2002-clint
55              - thead,th1520-clint
56          - const: thead,c900-clint
57      - items:
58          - const: sifive,clint0
59          - const: riscv,clint0
60        deprecated: true
61        description: For the QEMU virt machine only
62
63    description:
64      Should be "<vendor>,<chip>-clint", followed by "sifive,clint<version>"
65      when compatible with a SiFive CLINT.  Please refer to
66      sifive-blocks-ip-versioning.txt for details regarding the latter.
67
68  reg:
69    maxItems: 1
70
71  interrupts-extended:
72    minItems: 1
73    maxItems: 4095
74
75  sifive,fine-ctr-bits:
76    maximum: 15
77    description: The width in bits of the fine counter.
78
79if:
80  properties:
81    compatible:
82      contains:
83        const: sifive,clint2
84then:
85  required:
86    - sifive,fine-ctr-bits
87else:
88  properties:
89    sifive,fine-ctr-bits: false
90
91additionalProperties: false
92
93required:
94  - compatible
95  - reg
96  - interrupts-extended
97
98examples:
99  - |
100    timer@2000000 {
101      compatible = "sifive,fu540-c000-clint", "sifive,clint0";
102      interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
103                            <&cpu2intc 3>, <&cpu2intc 7>,
104                            <&cpu3intc 3>, <&cpu3intc 7>,
105                            <&cpu4intc 3>, <&cpu4intc 7>;
106      reg = <0x2000000 0x10000>;
107    };
108...
109