xref: /linux/Documentation/devicetree/bindings/timer/sifive,clint.yaml (revision 0a94608f0f7de9b1135ffea3546afe68eafef57f) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/timer/sifive,clint.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: SiFive Core Local Interruptor
8
9maintainers:
10  - Palmer Dabbelt <palmer@dabbelt.com>
11  - Anup Patel <anup.patel@wdc.com>
12
13description:
14  SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15  Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16  interrupts. It directly connects to the timer and inter-processor interrupt
17  lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
18  interrupt controller is the parent interrupt controller for CLINT device.
19  The clock frequency of CLINT is specified via "timebase-frequency" DT
20  property of "/cpus" DT node. The "timebase-frequency" DT property is
21  described in Documentation/devicetree/bindings/riscv/cpus.yaml
22
23properties:
24  compatible:
25    items:
26      - enum:
27          - sifive,fu540-c000-clint
28          - starfive,jh7100-clint
29          - canaan,k210-clint
30      - const: sifive,clint0
31
32    description:
33      Should be "<vendor>,<chip>-clint" and "sifive,clint<version>".
34      Supported compatible strings are -
35      "sifive,fu540-c000-clint" for the SiFive CLINT v0 as integrated
36      onto the SiFive FU540 chip, "canaan,k210-clint" for the SiFive
37      CLINT v0 as integrated onto the Canaan Kendryte K210 chip, and
38      "sifive,clint0" for the SiFive CLINT v0 IP block with no chip
39      integration tweaks.
40      Please refer to sifive-blocks-ip-versioning.txt for details
41
42  reg:
43    maxItems: 1
44
45  interrupts-extended:
46    minItems: 1
47    maxItems: 4095
48
49additionalProperties: false
50
51required:
52  - compatible
53  - reg
54  - interrupts-extended
55
56examples:
57  - |
58    timer@2000000 {
59      compatible = "sifive,fu540-c000-clint", "sifive,clint0";
60      interrupts-extended = <&cpu1intc 3>, <&cpu1intc 7>,
61                            <&cpu2intc 3>, <&cpu2intc 7>,
62                            <&cpu3intc 3>, <&cpu3intc 7>,
63                            <&cpu4intc 3>, <&cpu4intc 7>;
64       reg = <0x2000000 0x10000>;
65    };
66...
67